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src/mem/packet.hh <http://reviews.gem5.org/r/1169/#comment3022> This transaction used to be used by the DMA engine when writing full blocks to memory (see http://repo.gem5.org/gem5/rev/4ac3d9486d6e). I see it's not used anymore since we put the I/O cache in place to deal with partial block writes (see http://repo.gem5.org/gem5/rev/ad0e792a5c78). I don't see anything in the cache code that treats full-block writes specially (other than writebacks, which are different because in that case the requester already had exclusive access). Does this mean the I/O cache is doing read-exclusive operations on every full-cache-block DMA? That seems bad. In other words, instead of getting rid of WriteInvalidateReq because it's not used, should we be trying to use it again? - Steve Reinhardt On May 2, 2012, 7:15 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1169/ > ----------------------------------------------------------- > > (Updated May 2, 2012, 7:15 a.m.) > > > Review request for Default. > > > Description > ------- > > Packet: Cleaning up packet command and attribute > > This patch removes unused commands and attributes from the packet to > avoid any confusion. It is part of an effort to clear up how and where > different commands and attributes are used. > > > Diffs > ----- > > src/mem/packet.hh 7f36d4436074 > src/mem/packet.cc 7f36d4436074 > > Diff: http://reviews.gem5.org/r/1169/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
