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src/cpu/checker/cpu_impl.hh <http://reviews.gem5.org/r/1195/#comment3109> Why aren't we skipping the ExtMachInst completely here, and just doing instPtr = thread->decoder.decode(pcState) ? src/cpu/inorder/resources/fetch_unit.cc <http://reviews.gem5.org/r/1195/#comment3112> same comment as above... this function name makes no sense in the modified context where the code doesn't mention extMachInst otherwise src/cpu/legiontrace.cc <http://reviews.gem5.org/r/1195/#comment3111> the concept of "extMachInst" is meaningless now, so this function name doesn't make sense in context. should it be decoderReady() or something like that? src/cpu/o3/fetch_impl.hh <http://reviews.gem5.org/r/1195/#comment3113> similar thing here... how is !extMachInstReady() at this point different from needMoreBytes()? The latter sounds more intuitively like what you want to call based on the name of the flag. - Steve Reinhardt On May 15, 2012, 5:56 a.m., Gabe Black wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1195/ > ----------------------------------------------------------- > > (Updated May 15, 2012, 5:56 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9009:769d2142cbd4 > --------------------------- > CPU: Merge the predecoder and decoder. > > These classes are always used together, and merging them will give the ISAs > more flexibility in how they cache things and manage the process. > > > Diffs > ----- > > src/arch/SConscript f681719e2e99 > src/arch/alpha/decoder.hh PRE-CREATION > src/arch/alpha/isa/main.isa f681719e2e99 > src/arch/alpha/predecoder.hh f681719e2e99 > src/arch/arm/SConscript f681719e2e99 > src/arch/arm/decoder.hh PRE-CREATION > src/arch/arm/decoder.cc PRE-CREATION > src/arch/arm/predecoder.hh f681719e2e99 > src/arch/arm/predecoder.cc f681719e2e99 > src/arch/arm/types.hh f681719e2e99 > src/arch/mips/decoder.hh PRE-CREATION > src/arch/mips/predecoder.hh f681719e2e99 > src/arch/power/decoder.hh PRE-CREATION > src/arch/sparc/decoder.hh PRE-CREATION > src/arch/sparc/predecoder.hh f681719e2e99 > src/arch/x86/SConscript f681719e2e99 > src/arch/x86/decoder.hh PRE-CREATION > src/arch/x86/decoder.cc PRE-CREATION > src/arch/x86/decoder_tables.cc PRE-CREATION > src/arch/x86/emulenv.cc f681719e2e99 > src/arch/x86/isa/decoder/one_byte_opcodes.isa f681719e2e99 > src/arch/x86/predecoder.hh f681719e2e99 > src/arch/x86/predecoder.cc f681719e2e99 > src/arch/x86/predecoder_tables.cc f681719e2e99 > src/arch/x86/types.hh f681719e2e99 > src/cpu/base.hh f681719e2e99 > src/cpu/checker/cpu.hh f681719e2e99 > src/cpu/checker/cpu_impl.hh f681719e2e99 > src/cpu/inorder/cpu.hh f681719e2e99 > src/cpu/inorder/cpu.cc f681719e2e99 > src/cpu/inorder/resources/cache_unit.hh f681719e2e99 > src/cpu/inorder/resources/cache_unit.cc f681719e2e99 > src/cpu/inorder/resources/fetch_unit.hh f681719e2e99 > src/cpu/inorder/resources/fetch_unit.cc f681719e2e99 > src/cpu/inorder/thread_context.hh f681719e2e99 > src/cpu/legiontrace.cc f681719e2e99 > src/cpu/o3/fetch.hh f681719e2e99 > src/cpu/o3/fetch_impl.hh f681719e2e99 > src/cpu/simple/atomic.cc f681719e2e99 > src/cpu/simple/base.hh f681719e2e99 > src/cpu/simple/base.cc f681719e2e99 > src/cpu/simple_thread.cc f681719e2e99 > > Diff: http://reviews.gem5.org/r/1195/diff/ > > > Testing > ------- > > > Thanks, > > Gabe Black > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
