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src/cpu/base.cc <http://reviews.gem5.org/r/1622/#comment3696> This won't work with FS mode. Actually I think it will crash src/cpu/base.cc <http://reviews.gem5.org/r/1622/#comment3697> What if the system isn't a ruby system, or a ruby system doesn't exist? src/cpu/base_dyn_inst.hh <http://reviews.gem5.org/r/1622/#comment3698> This code is only required for the O3 CPU, if you haven't tested it are you comfortable adding it to the repository? src/cpu/simple/atomic.hh <http://reviews.gem5.org/r/1622/#comment3699> Perhaps if the cpu is x86? I'm not sure we want to slow the sytem down by processing snoops in the simple cpu if we don't need to src/cpu/simple/timing.hh <http://reviews.gem5.org/r/1622/#comment3700> same as atomic src/cpu/simple/timing.cc <http://reviews.gem5.org/r/1622/#comment3701> Perhaps a isa traits so that this can be skipped entirely in other isas? - Ali Saidi On Jan. 14, 2013, 10:57 a.m., Derek Hower wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1622/ > ----------------------------------------------------------- > > (Updated Jan. 14, 2013, 10:57 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9468:1712e13b7a5d > --------------------------- > x86 isa: This patch attempts an implementation at mwait. > > This patch takes advantage of the fact that Ruby protocols forward cache > line evictions to the CPU to keep the LSQ in the O3 CPU consistent. > > Mwait works as follows: > 1. A cpu monitors an address of interest (monitor instruction) > 2. A cpu calls mwait - this loads the cache line into that cpu's cache. > 3. The cpu goes to sleep. > 4. When another processor requests write permission for the line, it is > evicted from the sleeping cpu's cache. This eviction is forwarded to the > sleeping cpu, which then wakes up. > > Notes: > 1. This implementation only works with ruby. > 2. It has not been tested with the O3 cpu. > 3. This patch was created by Marc Orr ([email protected]) > > > Diffs > ----- > > configs/ruby/MESI_CMP_directory.py 794711cac18b0b5b47782675d45b886f2c31449c > configs/ruby/MI_example.py 794711cac18b0b5b47782675d45b886f2c31449c > configs/ruby/MOESI_CMP_directory.py > 794711cac18b0b5b47782675d45b886f2c31449c > configs/ruby/MOESI_CMP_token.py 794711cac18b0b5b47782675d45b886f2c31449c > configs/ruby/MOESI_hammer.py 794711cac18b0b5b47782675d45b886f2c31449c > configs/ruby/Ruby.py 794711cac18b0b5b47782675d45b886f2c31449c > src/arch/x86/isa/decoder/two_byte_opcodes.isa > 794711cac18b0b5b47782675d45b886f2c31449c > src/arch/x86/isa/formats/formats.isa > 794711cac18b0b5b47782675d45b886f2c31449c > src/arch/x86/isa/formats/monitor_mwait.isa PRE-CREATION > src/cpu/SConscript 794711cac18b0b5b47782675d45b886f2c31449c > src/cpu/base.hh 794711cac18b0b5b47782675d45b886f2c31449c > src/cpu/base.cc 794711cac18b0b5b47782675d45b886f2c31449c > src/cpu/base_dyn_inst.hh 794711cac18b0b5b47782675d45b886f2c31449c > src/cpu/simple/atomic.hh 794711cac18b0b5b47782675d45b886f2c31449c > src/cpu/simple/base.cc 794711cac18b0b5b47782675d45b886f2c31449c > src/cpu/simple/timing.hh 794711cac18b0b5b47782675d45b886f2c31449c > src/cpu/simple/timing.cc 794711cac18b0b5b47782675d45b886f2c31449c > > Diff: http://reviews.gem5.org/r/1622/diff/ > > > Testing > ------- > > > Thanks, > > Derek Hower > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
