> On Jan. 14, 2013, 11:07 a.m., Ali Saidi wrote: > > > > Marc Orr wrote: > Thanks for the comments. I'm working on a second revision of this patch > to address the concerns brought up. I'll send it to Derek so he can update > the diff when I am done. > > * The version posted does not support the o3 model. I've already fixed > this in the version that I will be sending to derek. > * I will look into expanding this to work in full system and hope to have > fixes in place when I send the updated diff to derek. > * The patch seems to work with the classic memory system (I have a simple > test that passes when I run the simulator without passing the --ruby flag, > but I need to further validate this as I have no experience with classic > memory). >
FYI, I did confirm that this patch works with the classic memory system. The comment for this patch should be updated to reflect that (i.e. delete the parts that say ruby only, takes advantage of ruby, etc.). The comment should also be updated by removing the part that says the patch has not been tested with O3. - Marc ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1622/#review3823 ----------------------------------------------------------- On Jan. 25, 2013, 2:15 p.m., Derek Hower wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1622/ > ----------------------------------------------------------- > > (Updated Jan. 25, 2013, 2:15 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9468:1712e13b7a5d > --------------------------- > x86 isa: This patch attempts an implementation at mwait. > > This patch takes advantage of the fact that Ruby protocols forward cache > line evictions to the CPU to keep the LSQ in the O3 CPU consistent. > > Mwait works as follows: > 1. A cpu monitors an address of interest (monitor instruction) > 2. A cpu calls mwait - this loads the cache line into that cpu's cache. > 3. The cpu goes to sleep. > 4. When another processor requests write permission for the line, it is > evicted from the sleeping cpu's cache. This eviction is forwarded to the > sleeping cpu, which then wakes up. > > Notes: > 1. This implementation only works with ruby. > 2. It has not been tested with the O3 cpu. > 3. This patch was created by Marc Orr ([email protected]) > > > Diffs > ----- > > configs/ruby/MESI_CMP_directory.py 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > configs/ruby/MI_example.py 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > configs/ruby/MOESI_CMP_directory.py > 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > configs/ruby/MOESI_CMP_token.py 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > configs/ruby/MOESI_hammer.py 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > configs/ruby/Ruby.py 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > src/arch/x86/isa/decoder/two_byte_opcodes.isa > 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > src/arch/x86/isa/formats/formats.isa > 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > src/arch/x86/isa/formats/monitor_mwait.isa PRE-CREATION > src/cpu/SConscript 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > src/cpu/base.hh 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > src/cpu/base.cc 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > src/cpu/base_dyn_inst.hh 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > src/cpu/o3/cpu.hh 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > src/cpu/o3/cpu.cc 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > src/cpu/simple/atomic.hh 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > src/cpu/simple/base.cc 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > src/cpu/simple/timing.hh 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > src/cpu/simple/timing.cc 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 > > Diff: http://reviews.gem5.org/r/1622/diff/ > > > Testing > ------- > > > Thanks, > > Derek Hower > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
