----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1622/ -----------------------------------------------------------
(Updated Jan. 25, 2013, 2:15 p.m.) Review request for Default. Changes ------- Updates from Marc: 1. I've tested and confirmed that this version works with all CPU models (including O3), and in both syscall emulation and full system. 2. I ran into minor issues testing the O3 in syscall emulation where I was running out of stack space. I think there is a bug somewhere in the simulator (or more likely m5threads), but I was able to hack around it for testing purposes. This issue is orthogonal to this patch, so I hope to not worry about it for now. 3. While mwait does work in full system, testing it was a nightmare. This is because interrupts from a hardware timer and system calls trigger wakeups frequently. In fact, wakeups are triggered so frequently, that I suspect something may be wrong with fully system mode (maybe the timer is not running at the correct speed?). Again, this potential issue is orthogonal to this patch. Description ------- Changeset 9468:1712e13b7a5d --------------------------- x86 isa: This patch attempts an implementation at mwait. This patch takes advantage of the fact that Ruby protocols forward cache line evictions to the CPU to keep the LSQ in the O3 CPU consistent. Mwait works as follows: 1. A cpu monitors an address of interest (monitor instruction) 2. A cpu calls mwait - this loads the cache line into that cpu's cache. 3. The cpu goes to sleep. 4. When another processor requests write permission for the line, it is evicted from the sleeping cpu's cache. This eviction is forwarded to the sleeping cpu, which then wakes up. Notes: 1. This implementation only works with ruby. 2. It has not been tested with the O3 cpu. 3. This patch was created by Marc Orr ([email protected]) Diffs (updated) ----- configs/ruby/MESI_CMP_directory.py 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 configs/ruby/MI_example.py 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 configs/ruby/MOESI_CMP_directory.py 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 configs/ruby/MOESI_CMP_token.py 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 configs/ruby/MOESI_hammer.py 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 configs/ruby/Ruby.py 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 src/arch/x86/isa/decoder/two_byte_opcodes.isa 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 src/arch/x86/isa/formats/formats.isa 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 src/arch/x86/isa/formats/monitor_mwait.isa PRE-CREATION src/cpu/SConscript 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 src/cpu/base.hh 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 src/cpu/base.cc 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 src/cpu/base_dyn_inst.hh 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 src/cpu/o3/cpu.hh 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 src/cpu/o3/cpu.cc 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 src/cpu/simple/atomic.hh 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 src/cpu/simple/base.cc 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 src/cpu/simple/timing.hh 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 src/cpu/simple/timing.cc 23c3e1c0e9e47c39733f7e267bf0b6a05b082059 Diff: http://reviews.gem5.org/r/1622/diff/ Testing ------- Thanks, Derek Hower _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
