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Review request for Default. Description ------- Changeset 9682:711b011ae617 --------------------------- ruby: add stats to .sm files, remove cache profiler This patch is a preview of the proposed to changes to the way cache statistics are collected in ruby. As of now, there is separate entity called CacheProfiler which holds statistical variables for caches. The CacheMemory class defines different functions for accessing the CacheProfiler. These functions are then invoked in the .sm files. I find this approach opaque and prone to error. Secondly, we probably should not be paying the cost of a function call for recording statistics. Instead, I am proposing to allow for accessing statistical variables in the .sm files. The collection would become transparent. Secondly, it would happen in place, so no function calls. This patch makes changes to the MESI CMP directory protocol to provide a preview of what changes would happen if we decide to go ahead with this. There are statements for incrementing demand misses and hits for instruction and data cache accesses. Diffs ----- configs/ruby/MESI_CMP_directory.py df8e64db0fd8 src/mem/protocol/MESI_CMP_directory-L1cache.sm df8e64db0fd8 src/mem/protocol/MESI_CMP_directory-L2cache.sm df8e64db0fd8 src/mem/protocol/RubySlicc_Types.sm df8e64db0fd8 src/mem/ruby/profiler/CacheProfiler.hh df8e64db0fd8 src/mem/ruby/profiler/CacheProfiler.cc df8e64db0fd8 src/mem/ruby/profiler/SConscript df8e64db0fd8 src/mem/ruby/system/CacheMemory.hh df8e64db0fd8 src/mem/ruby/system/CacheMemory.cc df8e64db0fd8 src/mem/slicc/ast/InfixOperatorExprAST.py df8e64db0fd8 src/mem/slicc/ast/OperatorExprAST.py PRE-CREATION src/mem/slicc/ast/__init__.py df8e64db0fd8 src/mem/slicc/parser.py df8e64db0fd8 src/mem/slicc/symbols/StateMachine.py df8e64db0fd8 Diff: http://reviews.gem5.org/r/1849/diff/ Testing ------- This is how the output would look like: system.ruby.l1_cntrl0.L1Dcache.demand_hits 82 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 11220 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11302 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Dcache.total_sw_prefetches 0 # Number of software prefetches system.ruby.l1_cntrl0.L1Dcache.total_hw_prefetches 0 # Number of hardware prefetches system.ruby.l1_cntrl0.L1Dcache.total_prefetches 0 # Number of prefetches system.ruby.l1_cntrl0.L1Dcache.num_data_array_reads 0 # number of data array reads system.ruby.l1_cntrl0.L1Dcache.num_data_array_writes 0 # number of data array writes system.ruby.l1_cntrl0.L1Dcache.num_tag_array_reads 0 # number of tag array reads system.ruby.l1_cntrl0.L1Dcache.num_tag_array_writes 0 # number of tag array writes system.ruby.l1_cntrl0.L1Dcache.num_tag_array_stalls 0 # number of stalls caused by tag array system.ruby.l1_cntrl0.L1Dcache.num_data_array_stalls 0 # number of stalls caused by data array system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 105 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 105 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.total_sw_prefetches 0 # Number of software prefetches system.ruby.l1_cntrl0.L1Icache.total_hw_prefetches 0 # Number of hardware prefetches system.ruby.l1_cntrl0.L1Icache.total_prefetches 0 # Number of prefetches system.ruby.l1_cntrl0.L1Icache.num_data_array_reads 0 # number of data array reads system.ruby.l1_cntrl0.L1Icache.num_data_array_writes 0 # number of data array writes system.ruby.l1_cntrl0.L1Icache.num_tag_array_reads 0 # number of tag array reads system.ruby.l1_cntrl0.L1Icache.num_tag_array_writes 0 # number of tag array writes system.ruby.l1_cntrl0.L1Icache.num_tag_array_stalls 0 # number of stalls caused by tag array system.ruby.l1_cntrl0.L1Icache.num_data_array_stalls 0 # number of stalls caused by data array Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
