> On May 13, 2013, 3:55 p.m., Andreas Hansson wrote: > > Overall it looks good to me. Are the resulting stats unchanged? > > Nilay Vaish wrote: > I have not ran the regression tests yet. But obviously the statistics > files would change since new stats are being added to stats.txt and > several are being removed ruby.stats. I think the miss > counts should remain the same for the protocols where they were being > collected before. The hit counts were not being collected, so that would > be an addition.
Sounds good. It would be nice to know that values don't change (or that the change is understood). - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1849/#review4336 ----------------------------------------------------------- On May 13, 2013, 9:20 a.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1849/ > ----------------------------------------------------------- > > (Updated May 13, 2013, 9:20 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9686:66375a5b9ece > --------------------------- > ruby: add stats to .sm files, remove cache profiler > This patch changes the way cache statistics are collected in ruby. > > As of now, there is separate entity called CacheProfiler which holds > statistical variables for caches. The CacheMemory class defines different > functions for accessing the CacheProfiler. These functions are then invoked > in the .sm files. I find this approach opaque and prone to error. Secondly, > we probably should not be paying the cost of a function call for recording > statistics. > > Instead, this patch allows for accessing statistical variables in the > .sm files. The collection would become transparent. Secondly, it would happen > in place, so no function calls. The patch also removes the CacheProfiler > class. > > > Diffs > ----- > > configs/ruby/MOESI_CMP_directory.py eb075b2b925a > configs/ruby/MOESI_CMP_token.py eb075b2b925a > src/mem/protocol/MESI_CMP_directory-L1cache.sm eb075b2b925a > src/mem/protocol/MESI_CMP_directory-L2cache.sm eb075b2b925a > src/mem/protocol/MI_example-cache.sm eb075b2b925a > src/mem/protocol/MOESI_CMP_directory-L1cache.sm eb075b2b925a > src/mem/protocol/MOESI_CMP_directory-L2cache.sm eb075b2b925a > src/mem/protocol/MOESI_CMP_token-L1cache.sm eb075b2b925a > src/mem/protocol/MOESI_CMP_token-L2cache.sm eb075b2b925a > src/mem/protocol/MOESI_hammer-cache.sm eb075b2b925a > src/mem/protocol/RubySlicc_Exports.sm eb075b2b925a > src/mem/protocol/RubySlicc_Types.sm eb075b2b925a > src/mem/ruby/profiler/CacheProfiler.hh eb075b2b925a > src/mem/ruby/profiler/CacheProfiler.cc eb075b2b925a > src/mem/ruby/profiler/Profiler.hh eb075b2b925a > src/mem/ruby/profiler/SConscript eb075b2b925a > src/mem/ruby/system/CacheMemory.hh eb075b2b925a > src/mem/ruby/system/CacheMemory.cc eb075b2b925a > src/mem/slicc/ast/InfixOperatorExprAST.py eb075b2b925a > src/mem/slicc/ast/OperatorExprAST.py PRE-CREATION > src/mem/slicc/ast/__init__.py eb075b2b925a > src/mem/slicc/parser.py eb075b2b925a > src/mem/slicc/symbols/StateMachine.py eb075b2b925a > > Diff: http://reviews.gem5.org/r/1849/diff/ > > > Testing > ------- > > This is how the output would look like: > > system.ruby.l1_cntrl0.L1Dcache.demand_hits 82 > # Number of cache demand hits > system.ruby.l1_cntrl0.L1Dcache.demand_misses 11220 > # Number of cache demand misses > system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11302 > # Number of cache demand accesses > system.ruby.l1_cntrl0.L1Dcache.total_sw_prefetches 0 > # Number of software prefetches > system.ruby.l1_cntrl0.L1Dcache.total_hw_prefetches 0 > # Number of hardware prefetches > system.ruby.l1_cntrl0.L1Dcache.total_prefetches 0 > # Number of prefetches > system.ruby.l1_cntrl0.L1Dcache.num_data_array_reads 0 > # number of data array reads > system.ruby.l1_cntrl0.L1Dcache.num_data_array_writes 0 > # number of data array writes > system.ruby.l1_cntrl0.L1Dcache.num_tag_array_reads 0 > # number of tag array reads > system.ruby.l1_cntrl0.L1Dcache.num_tag_array_writes 0 > # number of tag array writes > system.ruby.l1_cntrl0.L1Dcache.num_tag_array_stalls 0 > # number of stalls caused by tag array > system.ruby.l1_cntrl0.L1Dcache.num_data_array_stalls 0 > # number of stalls caused by data array > system.ruby.l1_cntrl0.L1Icache.demand_hits 0 > # Number of cache demand hits > system.ruby.l1_cntrl0.L1Icache.demand_misses 105 > # Number of cache demand misses > system.ruby.l1_cntrl0.L1Icache.demand_accesses 105 > # Number of cache demand accesses > system.ruby.l1_cntrl0.L1Icache.total_sw_prefetches 0 > # Number of software prefetches > system.ruby.l1_cntrl0.L1Icache.total_hw_prefetches 0 > # Number of hardware prefetches > system.ruby.l1_cntrl0.L1Icache.total_prefetches 0 > # Number of prefetches > system.ruby.l1_cntrl0.L1Icache.num_data_array_reads 0 > # number of data array reads > system.ruby.l1_cntrl0.L1Icache.num_data_array_writes 0 > # number of data array writes > system.ruby.l1_cntrl0.L1Icache.num_tag_array_reads 0 > # number of tag array reads > system.ruby.l1_cntrl0.L1Icache.num_tag_array_writes 0 > # number of tag array writes > system.ruby.l1_cntrl0.L1Icache.num_tag_array_stalls 0 > # number of stalls caused by tag array > system.ruby.l1_cntrl0.L1Icache.num_data_array_stalls 0 > # number of stalls caused by data array > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
