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(Updated June 29, 2013, 10:44 p.m.) Review request for Default. Changes ------- Use Param.MemorySize for device_rowbuffer_size. Repository: gem5 Description ------- This patch gets rid of bytesPerCacheLine parameter and makes the DRAM configuration separate from cache line size. Instead of bytesPerCacheLine, I define a parameter for DRAM called burst_length. The burst_length parameter shows the length of a DRAM device burst in bits. Also, I replace lines_per_rowbuffer with device_rowbuffer_size to improve code portablity. Updates: - a burst length in beats for each memory type. - an interface width for each memory type. - the memory controller model is extended to reason about "system" packets vs "dram" packets and assemble the responses properly. It means that system packets larger than a full burst are split into multiple dram packets. Diffs (updated) ----- src/mem/SimpleDRAM.py UNKNOWN src/mem/simple_dram.hh UNKNOWN src/mem/simple_dram.cc UNKNOWN Diff: http://reviews.gem5.org/r/1927/diff/ Testing ------- None Thanks, Amin Farmahini _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
