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Ship it! Some very minor comments, then it's good to go. Have you run a complete regression with this patch? I'll kick one off just in case. src/mem/SimpleDRAM.py <http://reviews.gem5.org/r/1927/#comment4286> Can skip the "in bytes". src/mem/SimpleDRAM.py <http://reviews.gem5.org/r/1927/#comment4287> DDR2 -> LPDDR2_S4 src/mem/simple_dram.cc <http://reviews.gem5.org/r/1927/#comment4288> Perhaps a stupid question, but is this entirely safe? I guess it is...just thinking in terms of types, assumptions on powers of two etc. src/mem/simple_dram.cc <http://reviews.gem5.org/r/1927/#comment4289> Do you perhaps want to add the device organisation here as well, i.e. 1x32, 8x8 etc. src/mem/simple_dram.cc <http://reviews.gem5.org/r/1927/#comment4290> Not sure we want to count the DRAM bursts here as the stat was primarily for the arrivals. Is totGap not for the "system" packets any longer? - Andreas Hansson On July 24, 2013, 5:39 a.m., Amin Farmahini wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1927/ > ----------------------------------------------------------- > > (Updated July 24, 2013, 5:39 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > This patch gets rid of bytesPerCacheLine parameter and makes the DRAM > configuration separate from cache line size. > Instead of bytesPerCacheLine, I define a parameter for DRAM called > burst_length. The burst_length parameter shows the length of a DRAM device > burst in bits. > Also, I replace lines_per_rowbuffer with device_rowbuffer_size to improve > code portablity. > > Updates: > - a burst length in beats for each memory type. > - an interface width for each memory type. > - the memory controller model is extended to reason about "system" packets vs > "dram" packets and assemble the responses properly. It means that system > packets larger than a full burst are split into multiple dram packets. > > > Diffs > ----- > > src/mem/SimpleDRAM.py UNKNOWN > src/mem/simple_dram.hh UNKNOWN > src/mem/simple_dram.cc UNKNOWN > > Diff: http://reviews.gem5.org/r/1927/diff/ > > > Testing > ------- > > None > > > Thanks, > > Amin Farmahini > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
