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src/cpu/kvm/x86_cpu.cc <http://reviews.gem5.org/r/2013/#comment4494> Just noticed a typo in "synchronization" here. - Steve Reinhardt On Sept. 19, 2013, 8:36 a.m., Andreas Sandberg wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2013/ > ----------------------------------------------------------- > > (Updated Sept. 19, 2013, 8:36 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9884:5032bc7bffb9 > --------------------------- > kvm: x86: Fix segment registers to make them VMX compatible > > There are cases when the segment registers in gem5 are not compatible > with VMX. This changeset works around all known such issues. Specifically: > > * The accessed bits in CS, SS, DD, ES, FS, GS are forced to 1. > * The busy bit in TR is forced to 1. > * The protection level of SS is forced to the same protection level as > CS. The difference /seems/ to be caused by a bug in gem5's x86 > implementation. > > > Diffs > ----- > > src/cpu/kvm/x86_cpu.cc PRE-CREATION > > Diff: http://reviews.gem5.org/r/2013/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Sandberg > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
