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Review request for Default. Summary (updated) ----------------- Different SimpleDRAM latency for read and write access Repository: gem5 Description (updated) ------- This patch allows specifying different SimpleDRAM latency for read and write access. (In the code, tCL parameter if for read latency and tCL_write is for write latency). Any feedback is welcomed^^ Diffs (updated) ----- src/mem/SimpleDRAM.py 5e8970397ab7 src/mem/simple_dram.hh 5e8970397ab7 src/mem/simple_dram.cc 5e8970397ab7 Diff: http://reviews.gem5.org/r/2109/diff/ Testing ------- Thanks, Sophiane SENNI _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
