> On Dec. 6, 2013, 3:54 p.m., Amin Farmahini wrote: > > I don't think having two different tCL values is a good idea. I would > > instead suggest adding tCWD and tWR. > > Andreas Hansson wrote: > Great idea Sophiane. I'll put another vote down for Amin's suggestion > though.
I should be able to get some patches up in the next week or so that add tWR, and make any further differentiation between read and write much easier. Stay tuned. - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2109/#review4825 ----------------------------------------------------------- On Dec. 6, 2013, 11:09 a.m., Sophiane SENNI wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2109/ > ----------------------------------------------------------- > > (Updated Dec. 6, 2013, 11:09 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > This patch allows specifying different SimpleDRAM latency for read and write > access. (In the code, tCL parameter if for read latency and tCL_write is for > write latency). > > Any feedback is welcomed^^ > > > Diffs > ----- > > src/mem/SimpleDRAM.py 5e8970397ab7 > src/mem/simple_dram.hh 5e8970397ab7 > src/mem/simple_dram.cc 5e8970397ab7 > > Diff: http://reviews.gem5.org/r/2109/diff/ > > > Testing > ------- > > > Thanks, > > Sophiane SENNI > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
