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With the last patches that went in, the DRAM controller now has e.g. tWR added to the constraints. Does that provide enough detail, or is there still a need for turning tCL into tWL and tRL? If so, it would be good to see an updated patch. - Andreas Hansson On Dec. 6, 2013, 11:09 a.m., Sophiane SENNI wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2109/ > ----------------------------------------------------------- > > (Updated Dec. 6, 2013, 11:09 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > This patch allows specifying different SimpleDRAM latency for read and write > access. (In the code, tCL parameter if for read latency and tCL_write is for > write latency). > > Any feedback is welcomed^^ > > > Diffs > ----- > > src/mem/SimpleDRAM.py 5e8970397ab7 > src/mem/simple_dram.hh 5e8970397ab7 > src/mem/simple_dram.cc 5e8970397ab7 > > Diff: http://reviews.gem5.org/r/2109/diff/ > > > Testing > ------- > > > Thanks, > > Sophiane SENNI > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
