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(Updated June 21, 2014, 10 a.m.) Review request for Default. Changes ------- Fixed bug that Nilay found, which arose when an ifetch got issued between the load and store parts of a locked RMW. The ifetch qould issue, but the first thing it does is try to invalidate the block out of the L1D cache to move to the L1I cache, and since the block was locked, the cache would deadlock. Now we explicitly track when a request has locked a block and defer any access that is not an unlock request. The O3 boot test Nilay was running now passes, with the addition of the patch at http://reviews.gem5.org/r/2302. Did some substantial cleanup on this patch in the process. Repository: gem5 Description (updated) ------- Changeset 10240:b01d667ec431 --------------------------- ruby: don't make O3 CPU squash on loads that hit outstanding requests Mismatch between O3 and Ruby in handling aliased requests: Ruby returns false when it sees aliased request or memory blocked. O3 squash and refetch when it sees false signal from Ruby. Fix: Merging readRequestTable and writeRequestTable in a single table that maps requesting address and all requests that are aliased with the address. This work was done while Binh was an intern at AMD Research. Diffs (updated) ----- src/mem/packet.cc b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 src/mem/protocol/RubySlicc_Exports.sm b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 src/mem/ruby/system/DMASequencer.hh b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 src/mem/ruby/system/DMASequencer.cc b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 src/mem/ruby/system/RubyPort.hh b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 src/mem/ruby/system/RubyPort.cc b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 src/mem/ruby/system/RubyPortProxy.hh b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 src/mem/ruby/system/RubyPortProxy.cc b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 src/mem/ruby/system/Sequencer.hh b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 src/mem/ruby/system/Sequencer.cc b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 Diff: http://reviews.gem5.org/r/2276/diff/ Testing ------- Thanks, Steve Reinhardt _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
