Nilay, Coalescing and buffering requests in the Sequencer is very important for good performance. As long as we have a per address interface between our CPU/GPU models and Ruby, we need to cache block optimizations in Ruby.
Brad -----Original Message----- From: gem5-dev [mailto:gem5-dev-boun...@gem5.org] On Behalf Of Nilay Vaish via gem5-dev Sent: Thursday, December 04, 2014 7:36 AM To: Nilay Vaish; Steve Reinhardt; Default Subject: Re: [gem5-dev] Review Request 2276: ruby: don't make O3 CPU squash on loads that hit outstanding requests ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2276/#review5621 ----------------------------------------------------------- Steve, is it all right to buffer requests in the Sequencer? I am not even in favor of having a sequencer and buffering requests makes it worse. src/mem/ruby/system/Sequencer.cc <http://reviews.gem5.org/r/2276/#comment5024> initialize to false? - Nilay Vaish On June 21, 2014, 5 p.m., Steve Reinhardt wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2276/ > ----------------------------------------------------------- > > (Updated June 21, 2014, 5 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10240:b01d667ec431 > --------------------------- > ruby: don't make O3 CPU squash on loads that hit outstanding requests > > Mismatch between O3 and Ruby in handling aliased requests: Ruby > returns false when it sees aliased request or memory blocked. O3 > squash and refetch when it sees false signal from Ruby. > > Fix: Merging readRequestTable and writeRequestTable in a single table > that maps requesting address and all requests that are aliased with > the address. > > This work was done while Binh was an intern at AMD Research. > > > Diffs > ----- > > src/mem/packet.cc b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 > src/mem/protocol/RubySlicc_Exports.sm > b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 > src/mem/ruby/system/DMASequencer.hh > b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 > src/mem/ruby/system/DMASequencer.cc > b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 > src/mem/ruby/system/RubyPort.hh b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 > src/mem/ruby/system/RubyPort.cc b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 > src/mem/ruby/system/RubyPortProxy.hh > b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 > src/mem/ruby/system/RubyPortProxy.cc > b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 > src/mem/ruby/system/Sequencer.hh b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 > src/mem/ruby/system/Sequencer.cc > b21b3aad6bd1d01ac8a4d8030479bbca417af8d1 > > Diff: http://reviews.gem5.org/r/2276/diff/ > > > Testing > ------- > > > Thanks, > > Steve Reinhardt > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
