----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2315/ -----------------------------------------------------------
(Updated July 17, 2014, 9:40 a.m.) Review request for Default. Changes ------- change summary line to meet gem5 commit requirements Summary (updated) ----------------- config, x86: Ensure that PCI devs get bridged to the memory bus Repository: gem5 Description (updated) ------- config, x86: Ensure that PCI devs get bridged to the memory bus This patch force IO device to be mapped to 0xC0000000-0xFFFF0000 by reserve anything between the end of memory and 3GB if memory is less than 3GB. It also statically bridge these address range to the IO bus, which guaranty access to pci address space will pass though bridge to iobus. Diffs (updated) ----- configs/common/FSConfig.py 878f2f30b12d38f619b80b5d80d52498946f6ad1 Diff: http://reviews.gem5.org/r/2315/diff/ Testing ------- Thanks, Jiuyue Ma _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
