----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2315/#review5203 -----------------------------------------------------------
Ship it! LGTM. The concern raised by Andreas doesn't really apply here as x86 already makes the assumption that there are 1 or 2 memory ranges (see for example the assert on near the top of makeLinuxX86System, line 500, in FSConfig.py). In the long term, we probably want to get rid of that assumption. - Andreas Sandberg On July 17, 2014, 10:40 a.m., Jiuyue Ma wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2315/ > ----------------------------------------------------------- > > (Updated July 17, 2014, 10:40 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > config, x86: Ensure that PCI devs get bridged to the memory bus > > This patch force IO device to be mapped to 0xC0000000-0xFFFF0000 by > reserve anything between the end of memory and 3GB if memory is less > than 3GB. It also statically bridge these address range to the IO bus, > which guaranty access to pci address space will pass though bridge to > iobus. > > > Diffs > ----- > > configs/common/FSConfig.py 878f2f30b12d38f619b80b5d80d52498946f6ad1 > > Diff: http://reviews.gem5.org/r/2315/diff/ > > > Testing > ------- > > > Thanks, > > Jiuyue Ma > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
