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Thanks for the input Amin. One high-level question: what is the main aim of the patch? Until now we have tried to keep the timing constraints to a minimum (without sacrificing fidelity). In general you could argue that tBURST can be used, rather than adding tCCD and then taking the max. Do you envision any use-cases where this is not the case? - Andreas Hansson On July 23, 2014, 10:16 p.m., Amin Farmahini wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2316/ > ----------------------------------------------------------- > > (Updated July 23, 2014, 10:16 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > This patch adds support for tCCD to the DRAM controller. > After changeset 10211: e084db2b1527 (Merge DRAM latency calculation and bank > state update), DRAM latency calculations has changed and that changeset > provides a rather simple way to incorporate the tCCD parameter into latency > calculations. > > > Diffs > ----- > > src/mem/DRAMCtrl.py UNKNOWN > src/mem/dram_ctrl.hh UNKNOWN > src/mem/dram_ctrl.cc UNKNOWN > > Diff: http://reviews.gem5.org/r/2316/diff/ > > > Testing > ------- > > None > > > Thanks, > > Amin Farmahini > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
