> On Sept. 25, 2014, 7:18 a.m., Andreas Hansson wrote: > > src/mem/ruby/slicc_interface/AbstractController.cc, line 58 > > <http://reviews.gem5.org/r/2422/diff/1/?file=41706#file41706line58> > > > > Should we not have one of these for every memory controller? Or am I > > missing something? > > > > Is there an 1:N mapping of RubyController to memory controllers? If so, > > I'd even argue to put a NoncoherentXBar in between and let that XBar deal > > with the interleaving between the "local" controllers/channels. > > Nilay Vaish wrote: > Yes, I am assuming that a single directory controller can be attached to > multiple > memory controllers. In my understanding the directory controller should > subsume the role that a NoncoherentXBar would play. This really comes > down > to how actual systems are / can be designed and I may be wrong due to my > lack > of experience. > > > Andreas Hansson wrote: > I agree that one directory controller could be connected to a number of > DRAM channels/controllers. I think the most elegant solution here is to have > a single MasterPort on the directory controller, and then use a > NoncoherentXBar to interleave across the channels. This is also consistent > with how we do it in the classic memory system when using more elaborate > system topologies (not part of the normal fs.py or se.py). > > Perhaps the best way is to proceed with what you have, and make this > change in a future patch?
I have made the changes as you suggested. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2422/#review5360 ----------------------------------------------------------- On Sept. 25, 2014, 4:47 a.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2422/ > ----------------------------------------------------------- > > (Updated Sept. 25, 2014, 4:47 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10424:dfa22eb664e9 > --------------------------- > ruby: drop ruby's memory controller, interface with classic's. > This patch is the final in the series. The whole series and this patch in > particular were written with the aim of dropping the memory controller in > the ruby memory system and interfacing ruby's controller to make of the > memory controller in the classic memory system. This is being done since > ruby's memory controller has not being kept up to date with the changes > going on in DRAMs. Classic's memory controller is more up to date and > supports multiple different types of DRAM. This also brings classic and > ruby ever more close. > > > Diffs > ----- > > configs/example/ruby_mem_test.py d96740732a61 > configs/example/ruby_random_test.py d96740732a61 > configs/example/se.py d96740732a61 > configs/ruby/MESI_Three_Level.py d96740732a61 > configs/ruby/MESI_Two_Level.py d96740732a61 > configs/ruby/MI_example.py d96740732a61 > configs/ruby/MOESI_CMP_directory.py d96740732a61 > configs/ruby/MOESI_CMP_token.py d96740732a61 > configs/ruby/MOESI_hammer.py d96740732a61 > configs/ruby/Ruby.py d96740732a61 > src/mem/protocol/MESI_Two_Level-dir.sm d96740732a61 > src/mem/protocol/MI_example-dir.sm d96740732a61 > src/mem/protocol/MOESI_CMP_directory-dir.sm d96740732a61 > src/mem/protocol/MOESI_CMP_token-dir.sm d96740732a61 > src/mem/protocol/MOESI_hammer-dir.sm d96740732a61 > src/mem/protocol/RubySlicc_Defines.sm d96740732a61 > src/mem/protocol/RubySlicc_Types.sm d96740732a61 > src/mem/ruby/SConscript d96740732a61 > src/mem/ruby/network/MessageBuffer.cc d96740732a61 > src/mem/ruby/slicc_interface/AbstractController.hh d96740732a61 > src/mem/ruby/slicc_interface/AbstractController.cc d96740732a61 > src/mem/ruby/slicc_interface/Controller.py d96740732a61 > src/mem/ruby/structures/Cache.py d96740732a61 > src/mem/ruby/structures/DirectoryMemory.py d96740732a61 > src/mem/ruby/structures/MemoryControl.hh d96740732a61 > src/mem/ruby/structures/MemoryControl.cc d96740732a61 > src/mem/ruby/structures/MemoryControl.py d96740732a61 > src/mem/ruby/structures/MemoryVector.hh d96740732a61 > src/mem/ruby/structures/RubyMemoryControl.hh d96740732a61 > src/mem/ruby/structures/RubyMemoryControl.cc d96740732a61 > src/mem/ruby/structures/RubyMemoryControl.py d96740732a61 > src/mem/ruby/structures/SConscript d96740732a61 > src/mem/ruby/system/RubySystem.py d96740732a61 > src/mem/ruby/system/System.hh d96740732a61 > src/mem/ruby/system/System.cc d96740732a61 > src/mem/slicc/symbols/StateMachine.py d96740732a61 > src/python/swig/pyobject.cc d96740732a61 > tests/configs/pc-simple-timing-ruby.py d96740732a61 > > Diff: http://reviews.gem5.org/r/2422/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
