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configs/ruby/Ruby.py <http://reviews.gem5.org/r/2422/#comment4893> I may have confused myself here, so let's see if I have gotten this right. On the highest level, we have a number of memory ranges in the system (system.mem_ranges). These are possibly of different size etc. Somehow, and this is where I am not sure how it's done, we interleave these ranges across the directory controllers. Is this done purely by looking at some fixed address bits across the ranges? Once we are at each directory controller, each such controller could in theory connect to more than a single channel of memory, and then we need to interleave once again, but now it gets complicated. The crossbar is now responsible for an interleaved range for every range in system.mem_ranges, and then we again stripe across a number of channels? This means the memory controller (and ultimately AbstractMemory) sees a number of striped ranges, and the crossbar is not responsible for a contiguous range, but rather a stripe from a contiguous range. Is that right? - Andreas Hansson On Sept. 30, 2014, 9:38 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2422/ > ----------------------------------------------------------- > > (Updated Sept. 30, 2014, 9:38 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10431:069084e2706e > --------------------------- > ruby: drop ruby's memory controller, interface with classic's. > This patch is the final in the series. The whole series and this patch in > particular were written with the aim of dropping the memory controller in > the ruby memory system and interfacing ruby's controller to make of the > memory controller in the classic memory system. This is being done since > ruby's memory controller has not being kept up to date with the changes > going on in DRAMs. Classic's memory controller is more up to date and > supports multiple different types of DRAM. This also brings classic and > ruby ever more close. > > > Diffs > ----- > > configs/example/fs.py 7a76e13f0101 > configs/example/ruby_mem_test.py 7a76e13f0101 > configs/example/ruby_random_test.py 7a76e13f0101 > configs/example/se.py 7a76e13f0101 > configs/ruby/MESI_Three_Level.py 7a76e13f0101 > configs/ruby/MESI_Two_Level.py 7a76e13f0101 > configs/ruby/MI_example.py 7a76e13f0101 > configs/ruby/MOESI_CMP_directory.py 7a76e13f0101 > configs/ruby/MOESI_CMP_token.py 7a76e13f0101 > configs/ruby/MOESI_hammer.py 7a76e13f0101 > configs/ruby/Ruby.py 7a76e13f0101 > src/mem/protocol/MESI_Two_Level-dir.sm 7a76e13f0101 > src/mem/protocol/MI_example-dir.sm 7a76e13f0101 > src/mem/protocol/MOESI_CMP_directory-dir.sm 7a76e13f0101 > src/mem/protocol/MOESI_CMP_token-dir.sm 7a76e13f0101 > src/mem/protocol/MOESI_hammer-dir.sm 7a76e13f0101 > src/mem/protocol/RubySlicc_Defines.sm 7a76e13f0101 > src/mem/protocol/RubySlicc_Types.sm 7a76e13f0101 > src/mem/ruby/SConscript 7a76e13f0101 > src/mem/ruby/network/MessageBuffer.cc 7a76e13f0101 > src/mem/ruby/slicc_interface/AbstractController.hh 7a76e13f0101 > src/mem/ruby/slicc_interface/AbstractController.cc 7a76e13f0101 > src/mem/ruby/slicc_interface/Controller.py 7a76e13f0101 > src/mem/ruby/structures/Cache.py 7a76e13f0101 > src/mem/ruby/structures/DirectoryMemory.py 7a76e13f0101 > src/mem/ruby/structures/MemoryControl.hh 7a76e13f0101 > src/mem/ruby/structures/MemoryControl.cc 7a76e13f0101 > src/mem/ruby/structures/MemoryControl.py 7a76e13f0101 > src/mem/ruby/structures/MemoryVector.hh 7a76e13f0101 > src/mem/ruby/structures/RubyMemoryControl.hh 7a76e13f0101 > src/mem/ruby/structures/RubyMemoryControl.cc 7a76e13f0101 > src/mem/ruby/structures/RubyMemoryControl.py 7a76e13f0101 > src/mem/ruby/structures/SConscript 7a76e13f0101 > src/mem/ruby/system/RubySystem.py 7a76e13f0101 > src/mem/ruby/system/System.hh 7a76e13f0101 > src/mem/ruby/system/System.cc 7a76e13f0101 > src/mem/slicc/symbols/StateMachine.py 7a76e13f0101 > src/python/swig/pyobject.cc 7a76e13f0101 > tests/configs/pc-simple-timing-ruby.py 7a76e13f0101 > > Diff: http://reviews.gem5.org/r/2422/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
