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(Updated Oct. 21, 2014, 10:02 p.m.) Review request for Default. Summary (updated) ----------------- ruby: interface with classic memory controller Repository: gem5 Description (updated) ------- Changeset 10502:9b5f1e86eec0 --------------------------- ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface. Diffs (updated) ----- configs/common/MemConfig.py ffe6ab7141ab configs/example/fs.py ffe6ab7141ab configs/example/ruby_mem_test.py ffe6ab7141ab configs/example/ruby_random_test.py ffe6ab7141ab configs/example/se.py ffe6ab7141ab configs/ruby/MESI_Three_Level.py ffe6ab7141ab configs/ruby/MESI_Two_Level.py ffe6ab7141ab configs/ruby/MI_example.py ffe6ab7141ab configs/ruby/MOESI_CMP_directory.py ffe6ab7141ab configs/ruby/MOESI_CMP_token.py ffe6ab7141ab configs/ruby/MOESI_hammer.py ffe6ab7141ab configs/ruby/Ruby.py ffe6ab7141ab src/mem/protocol/MESI_Two_Level-dir.sm ffe6ab7141ab src/mem/protocol/MI_example-dir.sm ffe6ab7141ab src/mem/protocol/MOESI_CMP_directory-dir.sm ffe6ab7141ab src/mem/protocol/MOESI_CMP_token-dir.sm ffe6ab7141ab src/mem/protocol/MOESI_hammer-dir.sm ffe6ab7141ab src/mem/protocol/RubySlicc_Defines.sm ffe6ab7141ab src/mem/protocol/RubySlicc_Types.sm ffe6ab7141ab src/mem/ruby/SConscript ffe6ab7141ab src/mem/ruby/network/MessageBuffer.cc ffe6ab7141ab src/mem/ruby/slicc_interface/AbstractController.hh ffe6ab7141ab src/mem/ruby/slicc_interface/AbstractController.cc ffe6ab7141ab src/mem/ruby/slicc_interface/Controller.py ffe6ab7141ab src/mem/ruby/structures/Cache.py ffe6ab7141ab src/mem/ruby/structures/DirectoryMemory.py ffe6ab7141ab src/mem/ruby/structures/MemoryControl.hh ffe6ab7141ab src/mem/ruby/structures/MemoryControl.cc ffe6ab7141ab src/mem/ruby/structures/MemoryControl.py ffe6ab7141ab src/mem/ruby/structures/MemoryNode.hh ffe6ab7141ab src/mem/ruby/structures/MemoryNode.cc ffe6ab7141ab src/mem/ruby/structures/MemoryVector.hh ffe6ab7141ab src/mem/ruby/structures/RubyMemoryControl.hh ffe6ab7141ab src/mem/ruby/structures/RubyMemoryControl.cc ffe6ab7141ab src/mem/ruby/structures/RubyMemoryControl.py ffe6ab7141ab src/mem/ruby/structures/SConscript ffe6ab7141ab src/mem/ruby/system/RubySystem.py ffe6ab7141ab src/mem/ruby/system/System.hh ffe6ab7141ab src/mem/ruby/system/System.cc ffe6ab7141ab src/mem/slicc/symbols/StateMachine.py ffe6ab7141ab src/python/swig/pyobject.cc ffe6ab7141ab tests/configs/pc-simple-timing-ruby.py ffe6ab7141ab Diff: http://reviews.gem5.org/r/2422/diff/ Testing ------- Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
