Sounds great. I will make sure there is a GDDR5 config for Joel et al once we converge on the details.
Andreas On 14/10/2014 11:39, "Nilay Vaish via gem5-dev" <[email protected]> wrote: >On Mon, 13 Oct 2014, Andreas Hansson via gem5-dev wrote: > >> Hi Nilay, >> >> Thanks for the clarification. I believe the RubyMemoryController is >> completely Pareto dominated by the vanilla DRAMCtrl module, but if there >> is any specific feature/setting missing I would be keen to know. >> >> If possible I would like to make sure we use the same controller as a >> default for all timing simulations (even if the other one would be >> maintained as a fallback). We could always make RubyMemoryControl a >> subclass of DRAMCtrl if Brad really wants it to remain in the code base. >> > > >I am ready to yield on this. We will switch all the regression tests and >config scripts to make use of DRAMCtrl. As of now, I am thinking of >letting RubyMemoryController inherit from AbstractMemory, just like >SimpleMemory and DRAMCtrl. > >_______________________________________________ >gem5-dev mailing list >[email protected] >http://m5sim.org/mailman/listinfo/gem5-dev > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
