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(Updated Nov. 24, 2014, 12:20 p.m.) Review request for Default. Summary (updated) ----------------- cpu: Move packet deallocation to recvTimingResp in the O3 CPU Repository: gem5 Description (updated) ------- Changeset 10574:1126acf9f3b6 --------------------------- cpu: Move packet deallocation to recvTimingResp in the O3 CPU Move the packet deallocations in the O3 CPU so that the completeDataAccess deals only with the LSQ specific parts and the generic recvTimingResp frees the packet in all other cases. Diffs (updated) ----- src/cpu/o3/lsq_impl.hh 426665ec11a9 src/cpu/o3/lsq_unit_impl.hh 426665ec11a9 Diff: http://reviews.gem5.org/r/2501/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
