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Ship it! Ship It! - Steve Reinhardt On Nov. 24, 2014, 4:20 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2501/ > ----------------------------------------------------------- > > (Updated Nov. 24, 2014, 4:20 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10574:1126acf9f3b6 > --------------------------- > cpu: Move packet deallocation to recvTimingResp in the O3 CPU > > Move the packet deallocations in the O3 CPU so that the completeDataAccess > deals only with the LSQ specific parts and the generic recvTimingResp frees > the > packet in all other cases. > > > Diffs > ----- > > src/cpu/o3/lsq_impl.hh 426665ec11a9 > src/cpu/o3/lsq_unit_impl.hh 426665ec11a9 > > Diff: http://reviews.gem5.org/r/2501/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
