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Review request for Default. Repository: gem5 Description ------- Changeset 10791:d5f41246ec2e --------------------------- cpu: o3: replace issueLatency with bool pipelined Currently, each op class has a parameter issueLat that denotes the cycles after which another op of the same class can be issued. As of now, this latency can either be one cycle (fully pipelined) or same as execution latency of the op (not at all pipelined). The fact that issueLat is a parameter of type Cycles makes one believe that it can be set to any value. To avoid the confusion, the parameter is being renamed as 'pipelined' with type boolean. If set to true, the op would execute in a fully pipelined fashion. Otherwise, it would execute in an unpipelined fashion. Diffs ----- src/cpu/func_unit.hh d1df075f3b71 src/cpu/func_unit.cc d1df075f3b71 src/cpu/o3/FuncUnitConfig.py d1df075f3b71 src/cpu/o3/fu_pool.hh d1df075f3b71 src/cpu/o3/fu_pool.cc d1df075f3b71 src/cpu/o3/inst_queue_impl.hh d1df075f3b71 configs/common/O3_ARM_v7a.py d1df075f3b71 src/cpu/FuncUnit.py d1df075f3b71 Diff: http://reviews.gem5.org/r/2745/diff/ Testing ------- Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
