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src/cpu/o3/FuncUnitConfig.py (line 52)
<http://reviews.gem5.org/r/2745/#comment5271>

    Perhaps this is not intentional, but the specific case highlights that it 
is in fact possible to have a value that is neither 1, nor the opLat.
    
    Is there really no case where we want to say an operation takes X cycles 
and a new operation can be started every Y, with Y < X and Y > 1?


- Andreas Hansson


On April 20, 2015, 4:49 p.m., Nilay Vaish wrote:
> 
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> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2745/
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> 
> (Updated April 20, 2015, 4:49 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> -------
> 
> Changeset 10791:d5f41246ec2e
> ---------------------------
> cpu: o3: replace issueLatency with bool pipelined
> 
> Currently, each op class has a parameter issueLat that denotes the cycles 
> after
> which another op of the same class can be issued.  As of now, this latency can
> either be one cycle (fully pipelined) or same as execution latency of the op
> (not at all pipelined).  The fact that issueLat is a parameter of type Cycles
> makes one believe that it can be set to any value.  To avoid the confusion, 
> the
> parameter is being renamed as 'pipelined' with type boolean.  If set to true,
> the op would execute in a fully pipelined fashion. Otherwise, it would execute
> in an unpipelined fashion.
> 
> 
> Diffs
> -----
> 
>   src/cpu/func_unit.hh d1df075f3b71 
>   src/cpu/func_unit.cc d1df075f3b71 
>   src/cpu/o3/FuncUnitConfig.py d1df075f3b71 
>   src/cpu/o3/fu_pool.hh d1df075f3b71 
>   src/cpu/o3/fu_pool.cc d1df075f3b71 
>   src/cpu/o3/inst_queue_impl.hh d1df075f3b71 
>   configs/common/O3_ARM_v7a.py d1df075f3b71 
>   src/cpu/FuncUnit.py d1df075f3b71 
> 
> Diff: http://reviews.gem5.org/r/2745/diff/
> 
> 
> Testing
> -------
> 
> 
> Thanks,
> 
> Nilay Vaish
> 
>

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