> On May 12, 2015, 4:33 a.m., Nilay Vaish wrote: > > I will think more about this. This is not at all what I would want to do.
I thought about this patch. It is not what I would have done had I wanted to define multiple structures that inherit from AbstractCacheEntry. In retrospect, the set of decisions where in we decided to implicitly pass cache and tbe entries around seem very bad. But I hardly think AMD is willing to do the work required to fix SLICC. I am OK with this patch getting committed. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2794/#review6146 ----------------------------------------------------------- On May 11, 2015, 10:21 p.m., Tony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2794/ > ----------------------------------------------------------- > > (Updated May 11, 2015, 10:21 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10851:88582222762b > --------------------------- > slicc: support for multiple cache entry types in the same state machine > > To have multiple Entry types (e.g., a cache Entry type and > a directory Entry type), just declare one of them as a secondary > type by using the pair 'main="false"', e.g.: > > structure(DirEntry, desc="...", interface="AbstractCacheEntry", > main="false") { > > ...and the primary type would be declared: > > structure(Entry, desc="...", interface="AbstractCacheEntry") { > > > Diffs > ----- > > src/mem/slicc/symbols/StateMachine.py > fbdaa08aaa426b9f4660c366f934ccb670d954ec > > Diff: http://reviews.gem5.org/r/2794/diff/ > > > Testing > ------- > > > Thanks, > > Tony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
