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Ship it! I can be ok with this for now. For future reference, I think I like what Nilay is suggesting in the email thread: There should be a way for a SLICC state machine to designate which entry type (descended from AbstractCacheEntry) is used in transition and action headers, but the designation should be done outside of the type declaration itself. This designation might require adding a keyword or adjusting the machine declaration header, which would require adjustments to existing protocols. However, I think this solution makes more sense than the way this patch handles it, because it would allow arbitrary inheritance of AbstractCacheEntry without any special flags in the type declaration. - Joel Hestness On May 11, 2015, 10:21 p.m., Tony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2794/ > ----------------------------------------------------------- > > (Updated May 11, 2015, 10:21 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10851:88582222762b > --------------------------- > slicc: support for multiple cache entry types in the same state machine > > To have multiple Entry types (e.g., a cache Entry type and > a directory Entry type), just declare one of them as a secondary > type by using the pair 'main="false"', e.g.: > > structure(DirEntry, desc="...", interface="AbstractCacheEntry", > main="false") { > > ...and the primary type would be declared: > > structure(Entry, desc="...", interface="AbstractCacheEntry") { > > > Diffs > ----- > > src/mem/slicc/symbols/StateMachine.py > fbdaa08aaa426b9f4660c366f934ccb670d954ec > > Diff: http://reviews.gem5.org/r/2794/diff/ > > > Testing > ------- > > > Thanks, > > Tony Gutierrez > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
