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(Updated Jan. 18, 2016, 7:46 p.m.) Review request for Default. Changes ------- This revision doesn't address any reviewer concerns, but it does update the old implementation to work with the latest tree (for those who are still downloading this manually). It may also fix a bug; there was a bug in one of our internal versions but I'm not sure if that bug made it out onto reviewboard or not. Repository: gem5 Description ------- Changeset 10745:9b84d1b570e3 --------------------------- mem: implement x86 locked accesses in timing-mode classic cache Add LockedRMW(Read|Write)(Req|Resp) commands. In timing mode, use a combination of clearing permission bits and leaving an MSHR in place to prevent accesses & snoops from touching a locked block between the read and write parts of an locked RMW sequence. Diffs (updated) ----- src/mem/packet.cc d06e5a6b4b7f05a642c3e2bee12cfeb130dede16 src/mem/cache/cache.cc d06e5a6b4b7f05a642c3e2bee12cfeb130dede16 src/mem/cache/mshr.hh d06e5a6b4b7f05a642c3e2bee12cfeb130dede16 src/mem/packet.hh d06e5a6b4b7f05a642c3e2bee12cfeb130dede16 Diff: http://reviews.gem5.org/r/2691/diff/ Testing ------- Thanks, Steve Reinhardt _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
