-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3502/
-----------------------------------------------------------
Review request for Default.
Repository: gem5
Description
-------
Split the hit latency into tag lookup latency and RAM access latency.
If the cache access mode is parallel ("sequential_access" parameter set to
"False"), tags and RAMs are accessed in parallel. Therefore, the hit latency is
the maximum latency between tag lookup latency and RAM access latency. On the
other hand, if the cache access mode is sequential ("sequential_access"
parameter set to "True"), tags and RAM are accessed sequentially. Therefore,
the hit latency is the sum of tag lookup latency plus RAM access latency.
Diffs
-----
configs/common/Caches.py 629fe6e6c781
src/mem/cache/BaseCache.py 629fe6e6c781
src/mem/cache/base.hh 629fe6e6c781
src/mem/cache/base.cc 629fe6e6c781
src/mem/cache/tags/Tags.py 629fe6e6c781
src/mem/cache/tags/base.hh 629fe6e6c781
src/mem/cache/tags/base.cc 629fe6e6c781
src/mem/cache/tags/base_set_assoc.hh 629fe6e6c781
src/mem/cache/tags/fa_lru.cc 629fe6e6c781
src/mem/cache/tags/fa_lru.hh 629fe6e6c781
Diff: http://reviews.gem5.org/r/3502/diff/
Testing
-------
Tested using --Debug-flags=Cache
Thanks,
Sophiane SENNI
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
