> On juin 16, 2016, 2:37 après-midi, Jason Lowe-Power wrote: > > Hi Sophiane, > > > > Thanks for the contribution. It looks like some of the patch doesn't apply > > cleanly in reviewboard. Did you use the hg postreview extension? It may > > also help to use the "-o" option on the extension. > > > > Cheers! > > Sophiane SENNI wrote: > Hi Jason, > > If I use the hg postreview extension (with the following command hg > postreview -o -u -e 3502), all the patch does not apply cleanly. > > Jason Lowe-Power wrote: > Make sure you're applying your patch on top of the most recent version of > gem5 (NOT gem5-stable). "hg incoming" and "hg pull" may be helpful. > > For instance, I believe BaseCache.py was renamed Cache.py in the last few > months (I don't remember exactly when).
For the current posted patch, I used the following command "hg diff -g", then I post the patch manually through reviewboard GUI. But using this method does not also work properly. As you noticed, some of the patch doesn't apply cleanly. - Sophiane ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3502/#review8413 ----------------------------------------------------------- On juin 16, 2016, 3:27 après-midi, Sophiane SENNI wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3502/ > ----------------------------------------------------------- > > (Updated juin 16, 2016, 3:27 après-midi) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10875:dd94e2606640 > --------------------------- > cache: Split the hit latency into tag lookup latency and RAM access latency > > If the cache access mode is parallel ("sequential_access" parameter set to > "False"), tags and RAMs are accessed in parallel. Therefore, the hit latency > is the maximum latency between tag lookup latency and RAM access latency. On > the other hand, if the cache access mode is sequential ("sequential_access" > parameter set to "True"), tags and RAM are accessed sequentially. Therefore, > the hit latency is the sum of tag lookup latency plus RAM access latency. > > > Diffs > ----- > > src/mem/cache/tags/fa_lru.cc UNKNOWN > src/mem/cache/tags/fa_lru.hh UNKNOWN > src/mem/cache/tags/base_set_assoc.hh UNKNOWN > src/mem/cache/tags/base.cc UNKNOWN > src/mem/cache/tags/base.hh UNKNOWN > src/mem/cache/tags/Tags.py UNKNOWN > src/mem/cache/base.hh UNKNOWN > src/mem/cache/base.cc UNKNOWN > src/mem/cache/BaseCache.py UNKNOWN > configs/common/Caches.py UNKNOWN > > Diff: http://reviews.gem5.org/r/3502/diff/ > > > Testing > ------- > > Tested using --Debug-flags=Cache > > > Thanks, > > Sophiane SENNI > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
