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src/cpu/kvm/base.cc <http://reviews.gem5.org/r/3619/#comment7506> I would prefer if we could keep the bypass caches check. Classic memory will definitely break if it isn't executing in cache bypass mode. I don't know if it is worth fixing, but I also don't like the fact that we can get really weird errors if this is removed. I'm not sure how this would interact with your Ruby patches though. You might need to add a timing cache bypass mode. src/cpu/kvm/base.cc (line 994) <http://reviews.gem5.org/r/3619/#comment7507> This is a bit of a nit, but would it be possible to move the state transitions to this switch statement instead of distributing them? I think that'll keep the state machine more maintainable in the future. You'll probably need to call the handler before updating the state in that case. - Andreas Sandberg On Aug. 17, 2016, 9:07 p.m., Michael LeBeane wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3619/ > ----------------------------------------------------------- > > (Updated Aug. 17, 2016, 9:07 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11561:4595cc3848fc > --------------------------- > kvm: Support timing accesses for KVM cpu > This patch enables timing accesses for KVM cpu. A new state, > RunningMMIOPending, is added to indicate that there are outstanding timing > requests generated by KVM in the system. KVM's tick() is disabled and the > simulation does not enter into KVM until all outstanding timing requests have > completed. The main motivation for this is to allow KVM CPU to perform MMIO > in Ruby, since Ruby does not support atomic accesses. > > > Diffs > ----- > > src/cpu/kvm/base.hh 91f58918a76abf1a1dedcaa70a9b95789da7b88c > src/cpu/kvm/base.cc 91f58918a76abf1a1dedcaa70a9b95789da7b88c > src/cpu/kvm/x86_cpu.cc 91f58918a76abf1a1dedcaa70a9b95789da7b88c > > Diff: http://reviews.gem5.org/r/3619/diff/ > > > Testing > ------- > > > Thanks, > > Michael LeBeane > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
