> On Aug. 18, 2016, 9:50 a.m., Andreas Sandberg wrote: > > src/cpu/kvm/base.cc, line 505 > > <http://reviews.gem5.org/r/3619/diff/2/?file=57574#file57574line505> > > > > I would prefer if we could keep the bypass caches check. Classic memory > > will definitely break if it isn't executing in cache bypass mode. I don't > > know if it is worth fixing, but I also don't like the fact that we can get > > really weird errors if this is removed. > > > > I'm not sure how this would interact with your Ruby patches though. You > > might need to add a timing cache bypass mode. > > Michael LeBeane wrote: > Just so I understand better, what issues are you concerned about if we > don't operate in bypass cache mode? It looks like caches won't be flushed > when entering KVM without being in bypass cache mode, so that's a concern. > Are you also concerned that other devices can write to the cache and KVM > won't see it? KVM itself only issues uncacheable IO requests, which > shouldn't matter whether bypass cache is enabled. > > For Ruby, we definately timing cache bypass mode, if only to make sure > caches are properly flushed when switching into KVM from Ruby-land. But > that's probably a seperate patch. > > Michael LeBeane wrote: > Turns out I was wrong, we don't need to flush Ruby caches because of the > backing store. But I will still need to introduce a timing_noncacheable mode > if you would like to keep this assertion, else I can't actually use this in > Ruby.
Devices (mainly DMAs) would definitely cause issues in classic since they typically sit behind an IO cache (and could potentially issue caching accesses). IIRC, there are also things we do differently in the interconnects. - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3619/#review8656 ----------------------------------------------------------- On Aug. 17, 2016, 9:07 p.m., Michael LeBeane wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3619/ > ----------------------------------------------------------- > > (Updated Aug. 17, 2016, 9:07 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11561:4595cc3848fc > --------------------------- > kvm: Support timing accesses for KVM cpu > This patch enables timing accesses for KVM cpu. A new state, > RunningMMIOPending, is added to indicate that there are outstanding timing > requests generated by KVM in the system. KVM's tick() is disabled and the > simulation does not enter into KVM until all outstanding timing requests have > completed. The main motivation for this is to allow KVM CPU to perform MMIO > in Ruby, since Ruby does not support atomic accesses. > > > Diffs > ----- > > src/cpu/kvm/base.hh 91f58918a76abf1a1dedcaa70a9b95789da7b88c > src/cpu/kvm/base.cc 91f58918a76abf1a1dedcaa70a9b95789da7b88c > src/cpu/kvm/x86_cpu.cc 91f58918a76abf1a1dedcaa70a9b95789da7b88c > > Diff: http://reviews.gem5.org/r/3619/diff/ > > > Testing > ------- > > > Thanks, > > Michael LeBeane > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
