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(Updated Jan. 26, 2017, 1:40 p.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 11761:58decfdf9c7b --------------------------- cpu: Result refactoring The Result union used to collect the result of an instruction is now a class of its own, with its constructor, and explicit casting methods for cleanliness. This is also a stepping stone to have vector registers, and instructions that produce a vector register as output. Change-Id: I6f40c11cb5e835d8b11f7804a4e967aff18025b9 Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com> Diffs (updated) ----- src/cpu/base_dyn_inst.hh 78ef8daecd81 src/cpu/checker/cpu.hh 78ef8daecd81 src/cpu/checker/cpu_impl.hh 78ef8daecd81 src/cpu/inst_res.hh PRE-CREATION Diff: http://reviews.gem5.org/r/3756/diff/ Testing ------- Builtin regressions Thanks, Rekai Gonzalez Alberquilla _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
