> On Jan. 19, 2017, 10:18 p.m., Jason Lowe-Power wrote: > > Does converting this to a class have any impact on performance? > > Rekai Gonzalez Alberquilla wrote: > The honest reply is I do not know. The long reply is: I did differential > performance analysis between the base of the 5 patches and each of the > patches. The 2nd or 3rd had a 2% slowdown, because I changed the rename table > to use a hash_map, so it mapped regIds to physRegIds. There used to be an > extra patch that reverted that. After applying all of them, test runs had a > marginal speedup (as the use of regIds allows for some more static > optimisations). Satisfied with that result, I merged the patch that reverted > the change into the 'generalize the use of regIds' patch, and I did not look > further into it. > If you think individual impact must be assesed, I can do a performance > regression.
Sounds good. It seemed possible that the added vtable lookup multiple times per instruction could have caused a performance drop. But since you checked, and it doesn't, the compiler must be smarter than me! - Jason ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3756/#review9285 ----------------------------------------------------------- On Jan. 26, 2017, 1:40 p.m., Rekai Gonzalez Alberquilla wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3756/ > ----------------------------------------------------------- > > (Updated Jan. 26, 2017, 1:40 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11761:58decfdf9c7b > --------------------------- > cpu: Result refactoring > > The Result union used to collect the result of an instruction is now a > class of its own, with its constructor, and explicit casting methods for > cleanliness. > > This is also a stepping stone to have vector registers, and instructions > that produce a vector register as output. > > Change-Id: I6f40c11cb5e835d8b11f7804a4e967aff18025b9 > Reviewed-by: Andreas Sandberg <[email protected]> > > > Diffs > ----- > > src/cpu/base_dyn_inst.hh 78ef8daecd81 > src/cpu/checker/cpu.hh 78ef8daecd81 > src/cpu/checker/cpu_impl.hh 78ef8daecd81 > src/cpu/inst_res.hh PRE-CREATION > > Diff: http://reviews.gem5.org/r/3756/diff/ > > > Testing > ------- > > Builtin regressions > > > Thanks, > > Rekai Gonzalez Alberquilla > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
