Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/7441
Change subject: arch-riscv: Update CSR implementations
......................................................................
arch-riscv: Update CSR implementations
This patch updates the CSRs to match the RISC-V privileged specification
version 1.10. It only modifies their initial values for SE mode, so only
U- and M-mode registers are implemented. As interrupts, faults, and
privilege levels are not yet supported, there are no meaninful side
effects that are implemented.
Note that even though S-mode is not implemented, placeholders for S-mode
registers are still included for future use (namely, FS mode).
Note also that this implementation trusts software to use the registers
properly. Access protection, readability, and writeability of registers
and register fields will come in a future patch.
Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
3 files changed, 252 insertions(+), 182 deletions(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 6091068..b9e9c95 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -64,9 +64,19 @@
miscRegFile[MISCREG_MVENDORID] = 0;
miscRegFile[MISCREG_MARCHID] = 0;
miscRegFile[MISCREG_MIMPID] = 0;
- miscRegFile[MISCREG_MISA] = 0x8000000000101129ULL;
+ miscRegFile[MISCREG_MCOUNTEREN] = 0x7;
+
+ misa.mxl = 0x2;
+ misa.extensions = 0x10112D;
+ mstatus.fs = 0x1;
+ mstatus.uxl = 0x2;
}
+bool
+ISA::hpmCounterEnabled(int misc_reg) const
+{
+ return (miscRegFile[MISCREG_MCOUNTEREN] & (1ULL << (misc_reg & 0x1F)))
0;
+}
MiscReg
ISA::readMiscRegNoEffect(int misc_reg) const
@@ -74,31 +84,47 @@
DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
switch (misc_reg) {
+ case MISCREG_MISA:
+ return misa;
+ case MISCREG_MHARTID:
+ warn("Use readMiscReg to read the mhartid CSR.");
+ return 0;
+ case MISCREG_MSTATUS:
+ return mstatus;
+ case MISCREG_MCYCLE:
+ case MISCREG_CYCLE:
+ warn("Use readMiscReg to read the cycle CSR.");
+ return 0;
+ case MISCREG_TIME:
+ if (!hpmCounterEnabled(MISCREG_TIME)) {
+ warn("CSR %s is not enabled.\n", MiscRegNames.at(misc_reg));
+ return 0;
+ }
+ return std::time(nullptr);
+ case MISCREG_MINSTRET:
+ case MISCREG_INSTRET:
+ warn("Use readMiscReg to read the instret CSR.");
+ return 0;
+ case MISCREG_MCYCLEH:
+ case MISCREG_CYCLEH:
+ warn("Use readMiscReg to read the cycleh CSR.");
+ return 0;
+ case MISCREG_TIMEH:
+ if (!hpmCounterEnabled(MISCREG_TIMEH)) {
+ warn("CSR %s is not enabled.\n", MiscRegNames.at(misc_reg));
+ return 0;
+ }
+ return std::time(nullptr) >> 32;
+ case MISCREG_MINSTRETH:
+ case MISCREG_INSTRETH:
+ warn("Use readMiscReg to read the instreth CSR.");
+ return 0;
case MISCREG_FFLAGS:
return bits(miscRegFile[MISCREG_FCSR], 4, 0);
case MISCREG_FRM:
return bits(miscRegFile[MISCREG_FCSR], 7, 5);
case MISCREG_FCSR:
return bits(miscRegFile[MISCREG_FCSR], 31, 0);
- case MISCREG_CYCLE:
- warn("Use readMiscReg to read the cycle CSR.");
- return 0;
- case MISCREG_TIME:
- return std::time(nullptr);
- case MISCREG_INSTRET:
- warn("Use readMiscReg to read the instret CSR.");
- return 0;
- case MISCREG_CYCLEH:
- warn("Use readMiscReg to read the cycleh CSR.");
- return 0;
- case MISCREG_TIMEH:
- return std::time(nullptr) >> 32;
- case MISCREG_INSTRETH:
- warn("Use readMiscReg to read the instreth CSR.");
- return 0;
- case MISCREG_MHARTID:
- warn("Use readMiscReg to read the mhartid CSR.");
- return 0;
default:
return miscRegFile[misc_reg];
}
@@ -108,24 +134,44 @@
ISA::readMiscReg(int misc_reg, ThreadContext *tc)
{
switch (misc_reg) {
- case MISCREG_INSTRET:
- DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
- MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
- return tc->getCpuPtr()->totalInsts();
+ case MISCREG_MHARTID:
+ return tc->cpuId() * tc->getCpuPtr()->numThreads + tc->threadId();
+ case MISCREG_MCYCLE:
case MISCREG_CYCLE:
DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
+ if (!hpmCounterEnabled(misc_reg)) {
+ warn("CSR %s is not enabled.\n", MiscRegNames.at(misc_reg));
+ return 0;
+ }
return tc->getCpuPtr()->curCycle();
- case MISCREG_INSTRETH:
+ case MISCREG_MINSTRET:
+ case MISCREG_INSTRET:
DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
- return tc->getCpuPtr()->totalInsts() >> 32;
+ if (!hpmCounterEnabled(misc_reg)) {
+ warn("CSR %s is not enabled.\n", MiscRegNames.at(misc_reg));
+ return 0;
+ }
+ return tc->getCpuPtr()->totalInsts();
+ case MISCREG_MCYCLEH:
case MISCREG_CYCLEH:
DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
+ if (!hpmCounterEnabled(misc_reg)) {
+ warn("CSR %s is not enabled.\n", MiscRegNames.at(misc_reg));
+ return 0;
+ }
return tc->getCpuPtr()->curCycle() >> 32;
- case MISCREG_MHARTID:
- return 0; // TODO: make this the hardware thread or cpu id
+ case MISCREG_MINSTRETH:
+ case MISCREG_INSTRETH:
+ DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
+ MiscRegNames.at(misc_reg), miscRegFile[misc_reg]);
+ if (hpmCounterEnabled(misc_reg)) {
+ warn("CSR %s is not enabled.\n", MiscRegNames.at(misc_reg));
+ return 0;
+ }
+ return tc->getCpuPtr()->totalInsts() >> 32;
default:
return readMiscRegNoEffect(misc_reg);
}
@@ -137,16 +183,20 @@
DPRINTF(RiscvMisc, "Setting CSR %s to 0x%016llx.\n",
MiscRegNames.at(misc_reg), val);
switch (misc_reg) {
+ case MISCREG_MISA:
+ misa = val;
+ break;
+ case MISCREG_MSTATUS:
+ mstatus = val;
+ break;
case MISCREG_FFLAGS:
- miscRegFile[MISCREG_FCSR] &= ~0x1F;
- miscRegFile[MISCREG_FCSR] |= bits(val, 4, 0);
+ replaceBits(miscRegFile[MISCREG_FCSR], 4, 0, val);
break;
case MISCREG_FRM:
- miscRegFile[MISCREG_FCSR] &= ~0x70;
- miscRegFile[MISCREG_FCSR] |= bits(val, 2, 0) << 5;
+ replaceBits(miscRegFile[MISCREG_FCSR], 7, 5, val);
break;
case MISCREG_FCSR:
- miscRegFile[MISCREG_FCSR] = bits(val, 7, 0);
+ replaceBits(miscRegFile[MISCREG_FCSR], 7, 0, val);
break;
default:
miscRegFile[misc_reg] = val;
@@ -161,7 +211,12 @@
warn("Ignoring write to read-only CSR.");
return;
}
- setMiscRegNoEffect(misc_reg, val);
+ switch (misc_reg)
+ {
+ default:
+ setMiscRegNoEffect(misc_reg, val);
+ break;
+ }
}
}
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 4f8b4dc..88251e0 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -43,6 +43,7 @@
#include "arch/riscv/registers.hh"
#include "arch/riscv/types.hh"
+#include "base/bitunion.hh"
#include "base/logging.hh"
#include "cpu/reg_class.hh"
#include "sim/sim_object.hh"
@@ -60,74 +61,61 @@
protected:
std::vector<MiscReg> miscRegFile;
+ BitUnion64(misa_t)
+ Bitfield<63, 62> mxl;
+ Bitfield<25, 0> extensions;
+ EndBitUnion(misa_t)
+ misa_t misa{0};
+
+ BitUnion64(mstatus_t)
+ Bitfield<63> sd;
+ Bitfield<35, 34> sxl;
+ Bitfield<33, 32> uxl;
+ Bitfield<22> tsr;
+ Bitfield<21> tw;
+ Bitfield<20> tvm;
+ Bitfield<19> mxr;
+ Bitfield<18> sum;
+ Bitfield<17> mprv;
+ Bitfield<16, 15> xs;
+ Bitfield<14, 13> fs;
+ Bitfield<12, 11> mpp;
+ Bitfield<8> spp;
+ Bitfield<7> mpie;
+ Bitfield<5> spie;
+ Bitfield<4> upie;
+ Bitfield<3> mie;
+ Bitfield<1> sie;
+ Bitfield<0> uie;
+ EndBitUnion(mstatus_t)
+ mstatus_t mstatus{0};
+
+ bool hpmCounterEnabled(int counter) const;
+
public:
typedef RiscvISAParams Params;
- void
- clear();
+ void clear();
- MiscReg
- readMiscRegNoEffect(int misc_reg) const;
+ MiscReg readMiscRegNoEffect(int misc_reg) const;
+ MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
+ void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
+ void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
- MiscReg
- readMiscReg(int misc_reg, ThreadContext *tc);
-
- void
- setMiscRegNoEffect(int misc_reg, const MiscReg &val);
-
- void
- setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
-
- RegId
- flattenRegId(const RegId ®Id) const
- {
- return regId;
- }
-
- int
- flattenIntIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenFloatIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecElemIndex(int reg) const
- {
- return reg;
- }
-
- // dummy
- int
- flattenCCIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenMiscIndex(int reg) const
- {
- return reg;
- }
+ RegId flattenRegId(const RegId ®Id) const { return regId; }
+ int flattenIntIndex(int reg) const { return reg; }
+ int flattenFloatIndex(int reg) const { return reg; }
+ int flattenVecIndex(int reg) const { return reg; }
+ int flattenVecElemIndex(int reg) const { return reg; }
+ int flattenCCIndex(int reg) const { return reg; }
+ int flattenMiscIndex(int reg) const { return reg; }
void startup(ThreadContext *tc) {}
/// Explicitly import the otherwise hidden startup
using SimObject::startup;
- const Params *
- params() const;
+ const Params *params() const;
ISA(Params *p);
};
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index a61554c..874f923 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -129,7 +129,7 @@
MISCREG_USCRATCH = 0x040,
MISCREG_UEPC = 0x041,
MISCREG_UCAUSE = 0x042,
- MISCREG_UBADADDR = 0x043,
+ MISCREG_UTVAL = 0x043,
MISCREG_UIP = 0x044,
MISCREG_FFLAGS = 0x001,
MISCREG_FRM = 0x002,
@@ -148,23 +148,13 @@
MISCREG_SIDELEG = 0x103,
MISCREG_SIE = 0x104,
MISCREG_STVEC = 0x105,
+ MISCREG_SCOUNTEREN = 0x106,
MISCREG_SSCRATCH = 0x140,
MISCREG_SEPC = 0x141,
MISCREG_SCAUSE = 0x142,
- MISCREG_SBADADDR = 0x143,
+ MISCREG_STVAL = 0x143,
MISCREG_SIP = 0x144,
- MISCREG_SPTBR = 0x180,
-
- MISCREG_HSTATUS = 0x200,
- MISCREG_HEDELEG = 0x202,
- MISCREG_HIDELEG = 0x203,
- MISCREG_HIE = 0x204,
- MISCREG_HTVEC = 0x205,
- MISCREG_HSCRATCH = 0x240,
- MISCREG_HEPC = 0x241,
- MISCREG_HCAUSE = 0x242,
- MISCREG_HBADADDR = 0x243,
- MISCREG_HIP = 0x244,
+ MISCREG_SATP = 0x180,
MISCREG_MVENDORID = 0xF11,
MISCREG_MARCHID = 0xF12,
@@ -176,23 +166,25 @@
MISCREG_MIDELEG = 0x303,
MISCREG_MIE = 0x304,
MISCREG_MTVEC = 0x305,
+ MISCREG_MCOUNTEREN = 0x306,
MISCREG_MSCRATCH = 0x340,
MISCREG_MEPC = 0x341,
MISCREG_MCAUSE = 0x342,
- MISCREG_MBADADDR = 0x343,
+ MISCREG_MTVAL = 0x343,
MISCREG_MIP = 0x344,
- MISCREG_MBASE = 0x380,
- MISCREG_MBOUND = 0x381,
- MISCREG_MIBASE = 0x382,
- MISCREG_MIBOUND = 0x383,
- MISCREG_MDBASE = 0x384,
- MISCREG_MDBOUND = 0x385,
+
+ MISCREG_PMPCFG0 = 0x3A0,
+ // MISCREG_PMPCFG1 only supported by RV32
+ MISCREG_PMPCFG2 = 0x3A2,
+ // MISCREG_PMPCFG3 only supported by RV32
+ MISCREG_PMPADDR_BASE = 0x3B0,
+
MISCREG_MCYCLE = 0xB00,
MISCREG_MINSTRET = 0xB02,
MISCREG_MHPMCOUNTER_BASE = 0xB03,
- MISCREG_MUCOUNTEREN = 0x320,
- MISCREG_MSCOUNTEREN = 0x321,
- MISCREG_MHCOUNTEREN = 0x322,
+ MISCREG_MCYCLEH = 0xB80,
+ MISCREG_MINSTRETH = 0xB82,
+ MISCREG_MHPMCOUNTERH_BASE = 0xB83,
MISCREG_MHPMEVENT_BASE = 0x323,
MISCREG_TSELECT = 0x7A0,
@@ -211,7 +203,7 @@
{MISCREG_USCRATCH, "uscratch"},
{MISCREG_UEPC, "uepc"},
{MISCREG_UCAUSE, "ucause"},
- {MISCREG_UBADADDR, "ubadaddr"},
+ {MISCREG_UTVAL, "utval"},
{MISCREG_UIP, "uip"},
{MISCREG_FFLAGS, "fflags"},
{MISCREG_FRM, "frm"},
@@ -219,13 +211,13 @@
{MISCREG_CYCLE, "cycle"},
{MISCREG_TIME, "time"},
{MISCREG_INSTRET, "instret"},
- {MISCREG_HPMCOUNTER_BASE + 0, "hpmcounter03"},
- {MISCREG_HPMCOUNTER_BASE + 1, "hpmcounter04"},
- {MISCREG_HPMCOUNTER_BASE + 2, "hpmcounter05"},
- {MISCREG_HPMCOUNTER_BASE + 3, "hpmcounter06"},
- {MISCREG_HPMCOUNTER_BASE + 4, "hpmcounter07"},
- {MISCREG_HPMCOUNTER_BASE + 5, "hpmcounter08"},
- {MISCREG_HPMCOUNTER_BASE + 6, "hpmcounter09"},
+ {MISCREG_HPMCOUNTER_BASE + 0, "hpmcounter3"},
+ {MISCREG_HPMCOUNTER_BASE + 1, "hpmcounter4"},
+ {MISCREG_HPMCOUNTER_BASE + 2, "hpmcounter5"},
+ {MISCREG_HPMCOUNTER_BASE + 3, "hpmcounter6"},
+ {MISCREG_HPMCOUNTER_BASE + 4, "hpmcounter7"},
+ {MISCREG_HPMCOUNTER_BASE + 5, "hpmcounter8"},
+ {MISCREG_HPMCOUNTER_BASE + 6, "hpmcounter9"},
{MISCREG_HPMCOUNTER_BASE + 7, "hpmcounter10"},
{MISCREG_HPMCOUNTER_BASE + 8, "hpmcounter11"},
{MISCREG_HPMCOUNTER_BASE + 9, "hpmcounter12"},
@@ -251,58 +243,48 @@
{MISCREG_CYCLEH, "cycleh"},
{MISCREG_TIMEH, "timeh"},
{MISCREG_INSTRETH, "instreth"},
- {MISCREG_HPMCOUNTERH_BASE + 0, "hpmcounterh03"},
- {MISCREG_HPMCOUNTERH_BASE + 1, "hpmcounterh04"},
- {MISCREG_HPMCOUNTERH_BASE + 2, "hpmcounterh05"},
- {MISCREG_HPMCOUNTERH_BASE + 3, "hpmcounterh06"},
- {MISCREG_HPMCOUNTERH_BASE + 4, "hpmcounterh07"},
- {MISCREG_HPMCOUNTERH_BASE + 5, "hpmcounterh08"},
- {MISCREG_HPMCOUNTERH_BASE + 6, "hpmcounterh09"},
- {MISCREG_HPMCOUNTERH_BASE + 7, "hpmcounterh10"},
- {MISCREG_HPMCOUNTERH_BASE + 8, "hpmcounterh11"},
- {MISCREG_HPMCOUNTERH_BASE + 9, "hpmcounterh12"},
- {MISCREG_HPMCOUNTERH_BASE + 10, "hpmcounterh13"},
- {MISCREG_HPMCOUNTERH_BASE + 11, "hpmcounterh14"},
- {MISCREG_HPMCOUNTERH_BASE + 12, "hpmcounterh15"},
- {MISCREG_HPMCOUNTERH_BASE + 13, "hpmcounterh16"},
- {MISCREG_HPMCOUNTERH_BASE + 14, "hpmcounterh17"},
- {MISCREG_HPMCOUNTERH_BASE + 15, "hpmcounterh18"},
- {MISCREG_HPMCOUNTERH_BASE + 16, "hpmcounterh19"},
- {MISCREG_HPMCOUNTERH_BASE + 17, "hpmcounterh20"},
- {MISCREG_HPMCOUNTERH_BASE + 18, "hpmcounterh21"},
- {MISCREG_HPMCOUNTERH_BASE + 19, "hpmcounterh22"},
- {MISCREG_HPMCOUNTERH_BASE + 20, "hpmcounterh23"},
- {MISCREG_HPMCOUNTERH_BASE + 21, "hpmcounterh24"},
- {MISCREG_HPMCOUNTERH_BASE + 22, "hpmcounterh25"},
- {MISCREG_HPMCOUNTERH_BASE + 23, "hpmcounterh26"},
- {MISCREG_HPMCOUNTERH_BASE + 24, "hpmcounterh27"},
- {MISCREG_HPMCOUNTERH_BASE + 25, "hpmcounterh28"},
- {MISCREG_HPMCOUNTERH_BASE + 26, "hpmcounterh29"},
- {MISCREG_HPMCOUNTERH_BASE + 27, "hpmcounterh30"},
- {MISCREG_HPMCOUNTERH_BASE + 28, "hpmcounterh31"},
+ {MISCREG_HPMCOUNTERH_BASE + 0, "hpmcounter3h"},
+ {MISCREG_HPMCOUNTERH_BASE + 1, "hpmcounter4h"},
+ {MISCREG_HPMCOUNTERH_BASE + 2, "hpmcounter5h"},
+ {MISCREG_HPMCOUNTERH_BASE + 3, "hpmcounter6h"},
+ {MISCREG_HPMCOUNTERH_BASE + 4, "hpmcounter7h"},
+ {MISCREG_HPMCOUNTERH_BASE + 5, "hpmcounter8h"},
+ {MISCREG_HPMCOUNTERH_BASE + 6, "hpmcounter9h"},
+ {MISCREG_HPMCOUNTERH_BASE + 7, "hpmcounter10h"},
+ {MISCREG_HPMCOUNTERH_BASE + 8, "hpmcounter11h"},
+ {MISCREG_HPMCOUNTERH_BASE + 9, "hpmcounter12h"},
+ {MISCREG_HPMCOUNTERH_BASE + 10, "hpmcounter13h"},
+ {MISCREG_HPMCOUNTERH_BASE + 11, "hpmcounter14h"},
+ {MISCREG_HPMCOUNTERH_BASE + 12, "hpmcounter15h"},
+ {MISCREG_HPMCOUNTERH_BASE + 13, "hpmcounter16h"},
+ {MISCREG_HPMCOUNTERH_BASE + 14, "hpmcounter17h"},
+ {MISCREG_HPMCOUNTERH_BASE + 15, "hpmcounter18h"},
+ {MISCREG_HPMCOUNTERH_BASE + 16, "hpmcounter19h"},
+ {MISCREG_HPMCOUNTERH_BASE + 17, "hpmcounter20h"},
+ {MISCREG_HPMCOUNTERH_BASE + 18, "hpmcounter21h"},
+ {MISCREG_HPMCOUNTERH_BASE + 19, "hpmcounter22h"},
+ {MISCREG_HPMCOUNTERH_BASE + 20, "hpmcounter23h"},
+ {MISCREG_HPMCOUNTERH_BASE + 21, "hpmcounter24h"},
+ {MISCREG_HPMCOUNTERH_BASE + 22, "hpmcounter25h"},
+ {MISCREG_HPMCOUNTERH_BASE + 23, "hpmcounter26h"},
+ {MISCREG_HPMCOUNTERH_BASE + 24, "hpmcounter27h"},
+ {MISCREG_HPMCOUNTERH_BASE + 25, "hpmcounter28h"},
+ {MISCREG_HPMCOUNTERH_BASE + 26, "hpmcounter29h"},
+ {MISCREG_HPMCOUNTERH_BASE + 27, "hpmcounter30h"},
+ {MISCREG_HPMCOUNTERH_BASE + 28, "hpmcounter31h"},
{MISCREG_SSTATUS, "sstatus"},
{MISCREG_SEDELEG, "sedeleg"},
{MISCREG_SIDELEG, "sideleg"},
{MISCREG_SIE, "sie"},
{MISCREG_STVEC, "stvec"},
+ {MISCREG_SCOUNTEREN, "scounteren"},
{MISCREG_SSCRATCH, "sscratch"},
{MISCREG_SEPC, "sepc"},
{MISCREG_SCAUSE, "scause"},
- {MISCREG_SBADADDR, "sbadaddr"},
+ {MISCREG_STVAL, "sbadaddr"},
{MISCREG_SIP, "sip"},
- {MISCREG_SPTBR, "sptbr"},
-
- {MISCREG_HSTATUS, "hstatus"},
- {MISCREG_HEDELEG, "hedeleg"},
- {MISCREG_HIDELEG, "hideleg"},
- {MISCREG_HIE, "hie"},
- {MISCREG_HTVEC, "htvec"},
- {MISCREG_HSCRATCH, "hscratch"},
- {MISCREG_HEPC, "hepc"},
- {MISCREG_HCAUSE, "hcause"},
- {MISCREG_HBADADDR, "hbadaddr"},
- {MISCREG_HIP, "hip"},
+ {MISCREG_SATP, "satp"},
{MISCREG_MVENDORID, "mvendorid"},
{MISCREG_MARCHID, "marchid"},
@@ -314,26 +296,43 @@
{MISCREG_MIDELEG, "mideleg"},
{MISCREG_MIE, "mie"},
{MISCREG_MTVEC, "mtvec"},
+ {MISCREG_MCOUNTEREN, "mcounteren"},
{MISCREG_MSCRATCH, "mscratch"},
{MISCREG_MEPC, "mepc"},
{MISCREG_MCAUSE, "mcause"},
- {MISCREG_MBADADDR, "mbadaddr"},
+ {MISCREG_MTVAL, "mtval"},
{MISCREG_MIP, "mip"},
- {MISCREG_MBASE, "mbase"},
- {MISCREG_MBOUND, "mbound"},
- {MISCREG_MIBASE, "mibase"},
- {MISCREG_MIBOUND, "mibound"},
- {MISCREG_MDBASE, "mdbase"},
- {MISCREG_MDBOUND, "mdbound"},
+
+ {MISCREG_PMPCFG0, "pmpcfg0"},
+ // pmpcfg1 only supported by RV32
+ {MISCREG_PMPCFG2, "pmpcfg2"},
+ // pmpcfg3 only supported by RV32
+ {MISCREG_PMPADDR_BASE + 0, "pmpaddr0"},
+ {MISCREG_PMPADDR_BASE + 1, "pmpaddr1"},
+ {MISCREG_PMPADDR_BASE + 2, "pmpaddr2"},
+ {MISCREG_PMPADDR_BASE + 3, "pmpaddr3"},
+ {MISCREG_PMPADDR_BASE + 4, "pmpaddr4"},
+ {MISCREG_PMPADDR_BASE + 5, "pmpaddr5"},
+ {MISCREG_PMPADDR_BASE + 6, "pmpaddr6"},
+ {MISCREG_PMPADDR_BASE + 7, "pmpaddr7"},
+ {MISCREG_PMPADDR_BASE + 8, "pmpaddr8"},
+ {MISCREG_PMPADDR_BASE + 9, "pmpaddr9"},
+ {MISCREG_PMPADDR_BASE + 10, "pmpaddr10"},
+ {MISCREG_PMPADDR_BASE + 11, "pmpaddr11"},
+ {MISCREG_PMPADDR_BASE + 12, "pmpaddr12"},
+ {MISCREG_PMPADDR_BASE + 13, "pmpaddr13"},
+ {MISCREG_PMPADDR_BASE + 14, "pmpaddr14"},
+ {MISCREG_PMPADDR_BASE + 15, "pmpaddr15"},
+
{MISCREG_MCYCLE, "mcycle"},
{MISCREG_MINSTRET, "minstret"},
- {MISCREG_MHPMCOUNTER_BASE + 0, "mhpmcounter03"},
- {MISCREG_MHPMCOUNTER_BASE + 1, "mhpmcounter04"},
- {MISCREG_MHPMCOUNTER_BASE + 2, "mhpmcounter05"},
- {MISCREG_MHPMCOUNTER_BASE + 3, "mhpmcounter06"},
- {MISCREG_MHPMCOUNTER_BASE + 4, "mhpmcounter07"},
- {MISCREG_MHPMCOUNTER_BASE + 5, "mhpmcounter08"},
- {MISCREG_MHPMCOUNTER_BASE + 6, "mhpmcounter09"},
+ {MISCREG_MHPMCOUNTER_BASE + 0, "mhpmcounter3"},
+ {MISCREG_MHPMCOUNTER_BASE + 1, "mhpmcounter4"},
+ {MISCREG_MHPMCOUNTER_BASE + 2, "mhpmcounter5"},
+ {MISCREG_MHPMCOUNTER_BASE + 3, "mhpmcounter6"},
+ {MISCREG_MHPMCOUNTER_BASE + 4, "mhpmcounter7"},
+ {MISCREG_MHPMCOUNTER_BASE + 5, "mhpmcounter8"},
+ {MISCREG_MHPMCOUNTER_BASE + 6, "mhpmcounter9"},
{MISCREG_MHPMCOUNTER_BASE + 7, "mhpmcounter10"},
{MISCREG_MHPMCOUNTER_BASE + 8, "mhpmcounter11"},
{MISCREG_MHPMCOUNTER_BASE + 9, "mhpmcounter12"},
@@ -356,9 +355,37 @@
{MISCREG_MHPMCOUNTER_BASE + 26, "mhpmcounter29"},
{MISCREG_MHPMCOUNTER_BASE + 27, "mhpmcounter30"},
{MISCREG_MHPMCOUNTER_BASE + 28, "mhpmcounter31"},
- {MISCREG_MUCOUNTEREN, "mucounteren"},
- {MISCREG_MSCOUNTEREN, "mscounteren"},
- {MISCREG_MHCOUNTEREN, "mhcounteren"},
+ {MISCREG_MCYCLEH, "mcycleh"},
+ {MISCREG_MINSTRETH, "minstreth"},
+ {MISCREG_MHPMCOUNTERH_BASE + 0, "mhpmcounter3h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 1, "mhpmcounter4h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 2, "mhpmcounter5h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 3, "mhpmcounter6h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 4, "mhpmcounter7h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 5, "mhpmcounter8h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 6, "mhpmcounter9h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 7, "mhpmcounter10h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 8, "mhpmcounter11h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 9, "mhpmcounter12h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 10, "mhpmcounter13h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 11, "mhpmcounter14h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 12, "mhpmcounter15h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 13, "mhpmcounter16h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 14, "mhpmcounter17h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 15, "mhpmcounter18h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 16, "mhpmcounter19h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 17, "mhpmcounter20h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 18, "mhpmcounter21h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 19, "mhpmcounter22h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 20, "mhpmcounter23h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 21, "mhpmcounter24h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 22, "mhpmcounter25h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 23, "mhpmcounter26h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 24, "mhpmcounter27h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 25, "mhpmcounter28h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 26, "mhpmcounter29h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 27, "mhpmcounter30h"},
+ {MISCREG_MHPMCOUNTERH_BASE + 28, "mhpmcounter31h"},
{MISCREG_MHPMEVENT_BASE + 0, "mhpmevent03"},
{MISCREG_MHPMEVENT_BASE + 1, "mhpmevent04"},
{MISCREG_MHPMEVENT_BASE + 2, "mhpmevent05"},
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a
Gerrit-Change-Number: 7441
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke <ar...@virginia.edu>
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