Hello Gabe Black, Tuan Ta, Robert Scheffel,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/7441
to look at the new patch set (#6).
Change subject: arch-riscv: Update CSR implementations
......................................................................
arch-riscv: Update CSR implementations
This patch updates the CSRs to match the RISC-V privileged specification
version 1.10. As interrupts, faults, and privilege levels are not yet
supported, there are no meaninful side effects that are implemented.
Supervisor mode will only be supported in FS mode, so S-mode registers
are guarded by checks that the system is in FS mode.
Note that this implementation trusts software to use the registers
properly. Access protection, readability, and writeability of registers
will come in a future patch.
Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a
---
M src/arch/riscv/insts/standard.cc
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/registers.hh
M src/arch/riscv/remote_gdb.cc
6 files changed, 886 insertions(+), 404 deletions(-)
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a
Gerrit-Change-Number: 7441
Gerrit-PatchSet: 6
Gerrit-Owner: Alec Roelke <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Robert Scheffel <[email protected]>
Gerrit-Reviewer: Tuan Ta <[email protected]>
Gerrit-MessageType: newpatchset
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