Hello Tuan Ta,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/7441
to look at the new patch set (#2).
Change subject: arch-riscv: Update CSR implementations
......................................................................
arch-riscv: Update CSR implementations
This patch updates the CSRs to match the RISC-V privileged specification
version 1.10. It only modifies their initial values. As interrupts,
faults, and privilege levels are not yet supported, there are no meaninful
side effects that are implemented. Supervisor mode will only be
supported in FS mode, so S-mode registers are guarded by checks that the
system is in FS mode.
Note that this implementation trusts software to use the registers
properly. Access protection, readability, and writeability of registers
and register fields will come in a future patch.
Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
3 files changed, 292 insertions(+), 182 deletions(-)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a
Gerrit-Change-Number: 7441
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-Reviewer: Tuan Ta <[email protected]>
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