Robert Scheffel has uploaded this change for review. ( https://gem5-review.googlesource.com/9061

Change subject: arch-riscv: enable rudimentary fs simulation
......................................................................

arch-riscv: enable rudimentary fs simulation

These changes enable a simple binary, that contains startup code, to be
simulated in full system mode. Therefore the RiscvSystem class was extended to load the binary into memory. Additionally, a new fault was implemented, that is executed once the CPU is initialized. This fault clears all interrupts and sets the pc to an implementation-defined reset vector.

Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
---
M src/arch/riscv/RiscvSystem.py
M src/arch/riscv/SConscript
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
M src/arch/riscv/interrupts.hh
M src/arch/riscv/system.cc
M src/arch/riscv/system.hh
M src/arch/riscv/tlb.cc
A src/arch/riscv/utility.cc
M src/arch/riscv/utility.hh
10 files changed, 201 insertions(+), 15 deletions(-)



diff --git a/src/arch/riscv/RiscvSystem.py b/src/arch/riscv/RiscvSystem.py
index c64e363..df0f964 100644
--- a/src/arch/riscv/RiscvSystem.py
+++ b/src/arch/riscv/RiscvSystem.py
@@ -29,9 +29,11 @@
 #
 # Authors: Alec Roelke

+from m5.params import *
 from System import System

 class RiscvSystem(System):
     type = 'RiscvSystem'
     cxx_header = 'arch/riscv/system.hh'
+    bootloader = Param.String("File, that contains the bootloader code")
     load_addr_mask = 0xFFFFFFFFFFFFFFFF
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 4655057..2482414 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -57,6 +57,7 @@
     Source('stacktrace.cc')
     Source('tlb.cc')
     Source('system.cc')
+    Source('utility.cc')

     Source('linux/process.cc')
     Source('linux/linux.cc')
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 4e44d43..5406aa1 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
+ * Copyright (c) 2018 TU Dresden
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,10 +28,13 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Alec Roelke
+ *          Robert Scheffel
  */
 #include "arch/riscv/faults.hh"

+#include "arch/riscv/system.hh"
 #include "arch/riscv/utility.hh"
+#include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "sim/debug.hh"
 #include "sim/full_system.hh"
@@ -56,6 +60,19 @@
     }
 }

+void Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
+{
+    if (FullSystem)
+    {
+        tc->getCpuPtr()->clearInterrupts(tc->threadId());
+        tc->clearArchRegs();
+    }
+
+    // Advance the PC to the implementation-defined reset vector
+    PCState pc = RiscvSystem::resetVect(tc);
+    tc->pcState(pc);
+}
+
 void
 UnknownInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
 {
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index 1e33b64..478bfd2 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
+ * Copyright (c) 2018 TU Dresden
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Alec Roelke
+ *          Robert Scheffel
  */

 #ifndef __ARCH_RISCV_FAULTS_HH__
@@ -104,6 +106,27 @@
     invoke(ThreadContext *tc, const StaticInstPtr &inst);
 };

+class Reset : public FaultBase
+{
+
+    public:
+        Reset()
+            : _name("reset")
+        {}
+
+        FaultName
+        name() const override
+        {
+            return _name;
+        }
+
+        void
+        invoke(ThreadContext *tc, const StaticInstPtr &inst =
+            StaticInst::nullStaticInstPtr) override;
+
+    private:
+        const FaultName _name;
+};

 class UnknownInstFault : public RiscvFault
 {
diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index cfb9a5b..0c1f906 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -32,6 +32,7 @@
 #define __ARCH_RISCV_INTERRUPT_HH__

 #include "base/logging.hh"
+#include "cpu/thread_context.hh"
 #include "params/RiscvInterrupts.hh"
 #include "sim/sim_object.hh"

@@ -78,13 +79,23 @@
     void
     clearAll()
     {
-        panic("Interrupts::clearAll not implemented.\n");
+        warn("Interrupts::clearAll not implemented.\n");
     }

     bool
     checkInterrupts(ThreadContext *tc) const
     {
-        panic("Interrupts::checkInterrupts not implemented.\n");
+        warn("Interrupts::checkInterrupts just rudimentary implemented");
+        /**
+ * read the machine interrupt register in order to check if interrupts
+         * are pending
+         * should be sufficient for now, as interrupts
+         * are not implemented at all
+         */
+        if (tc->readMiscReg(MISCREG_MIP))
+            return true;
+
+        return false;
     }

     Fault
diff --git a/src/arch/riscv/system.cc b/src/arch/riscv/system.cc
index 835fc97..425fe7c 100644
--- a/src/arch/riscv/system.cc
+++ b/src/arch/riscv/system.cc
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2018 TU Dresden
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,6 +30,7 @@
  * Authors: Ali Saidi
  *          Nathan Binkert
  *          Jaidev Patwardhan
+ *          Robert Scheffel
  */

 #include "arch/riscv/system.hh"
@@ -44,12 +46,55 @@

 using namespace LittleEndianGuest;

-RiscvSystem::RiscvSystem(Params *p) : System(p)
+RiscvSystem::RiscvSystem(Params *p)
+    : System(p),
+      _resetVect(0)
 {
+    bootloaderSymtab = new SymbolTable;
+
+    // load bootloader code into memory
+    bootloader = createObjectFile(p->bootloader);
+    if (bootloader == NULL) {
+         fatal("Could not load bootloader file %s", p->bootloader);
+    }
+
+    // load symbols
+    if (!bootloader->loadGlobalSymbols(bootloaderSymtab)) {
+        panic("Could not load bootloader symbols\n");
+    }
+
+    if (!bootloader->loadLocalSymbols(bootloaderSymtab)) {
+        panic("Could not load bootloader symbols\n");
+    }
+
+    _resetVect = bootloader->entryPoint();
 }

 RiscvSystem::~RiscvSystem()
 {
+    delete bootloaderSymtab;
+    delete bootloader;
+}
+
+void
+RiscvSystem::initState()
+{
+    // Call the initialisation of the super class
+    System::initState();
+
+    // load program sections into memory
+    if (!bootloader->loadSections(physProxy)) {
+        warn("could not load sections to memory");
+    }
+}
+
+/**
+ * Return the reset vector.
+ */
+Addr
+RiscvSystem::resetVect(ThreadContext* tc)
+{
+    return dynamic_cast<RiscvSystem *>(tc->getSystemPtr())->resetVect();
 }

 Addr
diff --git a/src/arch/riscv/system.hh b/src/arch/riscv/system.hh
index aa5eaaa..4f3a2ac 100644
--- a/src/arch/riscv/system.hh
+++ b/src/arch/riscv/system.hh
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2018 TU Dresden
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,6 +30,7 @@
  * Authors: Ali Saidi
  *          Nathan Binkert
  *          Jaidev Patwardhan
+ *          Robert Scheffel
  */

 #ifndef __ARCH_RISCV_SYSTEM_HH__
@@ -47,13 +49,32 @@

 class RiscvSystem : public System
 {
+  protected:
+    // bootloader object file
+    ObjectFile *bootloader;
+
+    // bootloader symbol table, not sure if needed
+    SymbolTable *bootloaderSymtab;
+
+    // entry point for simulation
+    Addr _resetVect;
+
   public:
     typedef RiscvSystemParams Params;
     RiscvSystem(Params *p);
     ~RiscvSystem();

+    // initialize the system
+    virtual void initState();
+
     virtual bool breakpoint();

+    // return reset address
+    Addr resetVect() const { return _resetVect; }
+
+    // return reset address of thread context
+    static Addr resetVect(ThreadContext* tc);
+
   public:

     /**
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 0c5962e..b92327f 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2001-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2018 TU Dresden
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -31,6 +32,7 @@
  *          Jaidev Patwardhan
  *          Zhengxing Li
  *          Deyuan Guo
+ *          Robert Scheffel
  */

 #include "arch/riscv/tlb.hh"
@@ -285,16 +287,34 @@
 Fault
 TLB::translateInst(RequestPtr req, ThreadContext *tc)
 {
-    if (FullSystem)
-        panic("translateInst not implemented in RISC-V.\n");
+    if (FullSystem) {
+        /**
+ * as we currently support bare metal only, we set the physical flag
+         * that means we treat all addresses as physical addresses
+         * no translation needed
+         */
+        req->setFlags(Request::PHYSICAL);
+    }

-    Process * p = tc->getProcessPtr();
+    if (req->getFlags() & Request::PHYSICAL) {
+        /**
+         * we simply set the virtual address to physical address
+         */
+        req->setPaddr(req->getVaddr());
+        /**
+         * check if the request is cacheable
+         * seems like this could have an impact on performance
+         */
+        return checkCacheability(req);
+    } else {
+        Process * p = tc->getProcessPtr();

-    Fault fault = p->pTable->translate(req);
-    if (fault != NoFault)
-        return fault;
+        Fault fault = p->pTable->translate(req);
+        if (fault != NoFault)
+            return fault;

-    return NoFault;
+        return NoFault;
+    }
 }

 Fault
diff --git a/src/arch/riscv/utility.cc b/src/arch/riscv/utility.cc
new file mode 100644
index 0000000..6e21a04
--- /dev/null
+++ b/src/arch/riscv/utility.cc
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018 TU Dresden
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Robert Scheffel
+ */
+
+#include "arch/riscv/utility.hh"
+
+#include "arch/riscv/faults.hh"
+
+namespace RiscvISA
+{
+
+void initCPU(ThreadContext *tc, int cpuId)
+{
+    static Fault reset = std::make_shared<Reset>();
+    reset->invoke(tc);
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index 78e9b91..6c0fcc1 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2013 ARM Limited
  * Copyright (c) 2014-2015 Sven Karlsson
+ * Copyright (c) 2018 TU Dresden
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -41,6 +42,7 @@
  * Authors: Andreas Hansson
  *          Sven Karlsson
  *          Alec Roelke
+ *          Robert Scheffel
  */

 #ifndef __ARCH_RISCV_UTILITY_HH__
@@ -117,6 +119,7 @@

 inline void startupCPU(ThreadContext *tc, int cpuId)
 {
+    tc->activate();
 }

 inline void
@@ -183,11 +186,10 @@
     return 0;
 }

-inline void
-initCPU(ThreadContext *, int cpuId)
-{
-    panic("initCPU not implemented for Riscv.\n");
-}
+/**
+ * init Cpu function
+ */
+void initCPU(ThreadContext *tc, int cpuId);

 } // namespace RiscvISA


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Gerrit-Change-Number: 9061
Gerrit-PatchSet: 1
Gerrit-Owner: Robert Scheffel <robert.scheff...@tu-dresden.de>
Gerrit-MessageType: newchange
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