Hello Tuan Ta, Alec Roelke,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/9061
to look at the new patch set (#5).
Change subject: arch-riscv: enable rudimentary fs simulation
......................................................................
arch-riscv: enable rudimentary fs simulation
These changes enable a simple binary, that contains startup code, to be
simulated in full system mode. Therefore the RiscvSystem class was extended
to load the binary into memory. Additionally, a new fault was implemented,
that is executed once the CPU is initialized. This fault clears all
interrupts and sets the pc to an implementation-defined reset vector.
Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
---
M src/arch/riscv/RiscvSystem.py
M src/arch/riscv/SConscript
A src/arch/riscv/bare_metal/system.cc
A src/arch/riscv/bare_metal/system.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
M src/arch/riscv/interrupts.hh
M src/arch/riscv/system.cc
M src/arch/riscv/system.hh
M src/arch/riscv/tlb.cc
A src/arch/riscv/utility.cc
M src/arch/riscv/utility.hh
12 files changed, 367 insertions(+), 34 deletions(-)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Gerrit-Change-Number: 9061
Gerrit-PatchSet: 5
Gerrit-Owner: Robert Scheffel <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-Reviewer: Robert Scheffel <[email protected]>
Gerrit-Reviewer: Tuan Ta <[email protected]>
Gerrit-CC: Christian Menard <[email protected]>
Gerrit-CC: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: newpatchset
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