Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17190
Change subject: mem-cache: Fix hit latency calculation order
......................................................................
mem-cache: Fix hit latency calculation order
Patch 6d8694a5fb5cfb905186249581cc6a3fde6cc38a changes the order
at which the access latency is calculated for non-writeback hits.
This order is incorrect, since the calculations must use the blk's
whenReady value before the access is satisfied.
Change-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17
Signed-off-by: Daniel <[email protected]>
---
M src/mem/cache/base.cc
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 9f708b3..14ee96d 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1159,8 +1159,6 @@
blk->isReadable())) {
// OK to satisfy access
incHitCount(pkt);
- satisfyRequest(pkt, blk);
- maintainClusivity(pkt->fromCache(), blk);
// Calculate access latency based on the need to access the data
array
if (pkt->isRead() || pkt->isWrite()) {
@@ -1169,6 +1167,9 @@
lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency);
}
+ satisfyRequest(pkt, blk);
+ maintainClusivity(pkt->fromCache(), blk);
+
return true;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17
Gerrit-Change-Number: 17190
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <[email protected]>
Gerrit-MessageType: newchange
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