Daniel Carvalho has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17190 )
Change subject: mem-cache: Fix write hit latency calculation order
......................................................................
mem-cache: Fix write hit latency calculation order
Patch 6d8694a5fb5cfb905186249581cc6a3fde6cc38a changes the order
at which the access latency is calculated for hits. This order
is incorrect, since the calculations must use the blk's whenReady
value before the access is satisfied.
Change-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17
Signed-off-by: Daniel <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17190
Reviewed-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Nikos Nikoleris <[email protected]>
Maintainer: Nikos Nikoleris <[email protected]>
---
M src/mem/cache/base.cc
1 file changed, 9 insertions(+), 8 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Giacomo Travaglini: Looks good to me, but someone else must approve
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 9f708b3..50622d7 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1065,15 +1065,15 @@
DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
incHitCount(pkt);
+ // A writeback searches for the block, then writes the data
+ lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency);
+
// When the packet metadata arrives, the tag lookup will be done
while
// the payload is arriving. Then the block will be ready to access
as
// soon as the fill is done
blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
std::max(cyclesToTicks(tag_latency),
(uint64_t)pkt->payloadDelay));
- // A writeback searches for the block, then writes the data
- lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency);
-
return true;
} else if (pkt->cmd == MemCmd::CleanEvict) {
// A CleanEvict does not need to access the data array
@@ -1143,15 +1143,15 @@
incHitCount(pkt);
+ // A writeback searches for the block, then writes the data
+ lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency);
+
// When the packet metadata arrives, the tag lookup will be done
while
// the payload is arriving. Then the block will be ready to access
as
// soon as the fill is done
blk->setWhenReady(clockEdge(fillLatency) + pkt->headerDelay +
std::max(cyclesToTicks(tag_latency),
(uint64_t)pkt->payloadDelay));
- // A writeback searches for the block, then writes the data
- lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency);
-
// if this a write-through packet it will be sent to cache
// below
return !pkt->writeThrough();
@@ -1159,8 +1159,6 @@
blk->isReadable())) {
// OK to satisfy access
incHitCount(pkt);
- satisfyRequest(pkt, blk);
- maintainClusivity(pkt->fromCache(), blk);
// Calculate access latency based on the need to access the data
array
if (pkt->isRead() || pkt->isWrite()) {
@@ -1169,6 +1167,9 @@
lat = calculateTagOnlyLatency(pkt->headerDelay, tag_latency);
}
+ satisfyRequest(pkt, blk);
+ maintainClusivity(pkt->fromCache(), blk);
+
return true;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17
Gerrit-Change-Number: 17190
Gerrit-PatchSet: 3
Gerrit-Owner: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-CC: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: merged
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