[gem5-dev] Change in gem5/gem5[develop]: cpu-simple: Ignore writes to the "zero" register.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49709 )

Change subject: cpu-simple: Ignore writes to the "zero" register.
......................................................................
cpu-simple: Ignore writes to the "zero" register.

Rather than constantly overwriting the "zero" register to return its
value to zero, just ignore writes to it.

We assume here that the "zero" register is a standard RegVal type
register (ie not bigger than 64 bits) and is accessed as such.

Change-Id: I06029b78103019c668647569c6037ca64a4d9c76
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49709
Maintainer: Gabe Black <gabe.bl...@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/cpu/minor/exec_context.hh
M src/cpu/simple/base.cc
M src/cpu/simple_thread.hh
3 files changed, 25 insertions(+), 4 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 0c01793..43dad26 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -97,7 +97,6 @@
         pcState(*inst->pc);
         setPredicate(inst->readPredicate());
         setMemAccPredicate(inst->readMemAccPredicate());
-        thread.setIntReg(zeroReg, 0);
     }

     ~ExecContext()
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 4cc8e1f..6db8025 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -307,9 +307,6 @@
     SimpleExecContext &t_info = *threadInfo[curThread];
     SimpleThread* thread = t_info.thread;

-    // maintain $r0 semantics
-    thread->setIntReg(zeroReg, 0);
-
     // resets predicates
     t_info.setPredicate(true);
     t_info.setMemAccPredicate(true);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 73c75ff..c2e620c 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -405,6 +405,9 @@
         auto &reg_file = regFiles[reg.classValue()];
         const auto &reg_class = reg_file.regClass;

+        if (reg.index() == reg_class.zeroReg())
+            return;
+
         DPRINTFV(reg_class.debug(), "Setting %s register %s (%d)  
to %#x.\n",
                 reg.className(), reg_class.regName(arch_reg), idx, val);
         reg_file.reg(idx) = val;
@@ -418,6 +421,9 @@
         auto &reg_file = regFiles[reg.classValue()];
         const auto &reg_class = reg_file.regClass;

+        if (reg.index() == reg_class.zeroReg())
+            return;
+
         DPRINTFV(reg_class.debug(), "Setting %s register %d to %#x.\n",
                 reg.className(), idx, val);
         reg_file.reg(idx) = val;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I06029b78103019c668647569c6037ca64a4d9c76
Gerrit-Change-Number: 49709
Gerrit-PatchSet: 53
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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