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FS#256 - . Two busses and a bridge can deadlock if the bridge between them has a full queue User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - . Two busses and a bridge can deadlock if the bridge between them has a full queue Task Type - Bug Category - Memory System Status - New Assigned To - Operating System - All Severity - Critical Priority - Normal Reported Version - 1.1 Due in Version - 2.0 Due Date - Undecided Percent Complete - 0% Details - Two busses and a bridge can deadlock if the bridge between them has a full queue in both directions because the bus only retries the device at the head of the retry list. For example in the picture below: Device <---- i/o bus ----> Bridge <----- mem bus -----> physical memory/cpu If the bridges queues are full and the device wants to write to physical memory and the cpu wants to write to the device at nearly the same time then the device attempts to write but its sendTiming fails because the Bridge queue is full -- the i/o bus is now blocked and will only retry the device. Similarly on the other side the cpu tries a sendTiming but it fails because the bridge queue is full -- the mem bus is now blocked and will only retry the cpu. Now both busses are blocked blocked waiting for requests that go to the bus bridge to be able to go, and the bus bridge is sitting around waiting for the ability for it to send data, but it never gets that ability since the bus is waiting for the cpu or device to send something. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/256 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
