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FS#208 - Implement Atomic Sparc Memory operations User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Implement Atomic Sparc Memory operations Task Type - Bug Category - Memory System Status - Assigned Assigned To - Kevin Lim Operating System - All Severity - Medium Priority - Normal Reported Version - 1.1 Due in Version - 2.1 Due Date - Undecided Percent Complete - 80% Details - Implement atomic memory operations (casa, casxa, ldstub, ldtx,etc). These instructions are all microcoded and need to be atomic so the first operation needs to lock the cache line or memory and until the second operation (a load or a store) loads/stores that line. Notes from Steve: I was probably the one who suggested to Gabe that these be microcoded in the first place, but now I'm wondering if it wouldn't make more sense to make these first-class memory operations (at least CAS and SWAP). Doing CAS and LDTX in a straightforward way would require changes to the request object (to allow both the compare and swap values to be sent for CAS, and to retrieve a 128-bit value for LDTX). If we don't want to change the request just for these we could still leave them as commands but use "special regs" in the cache. For example, CAS could consist of two memory operations, "set compare value" (which sends a value like a store) and then the actual CAS. Similarly the base LDTX could return half of the value and put the other half in a "cache reg", then a second operation could just read that reg. Since these ops would be part of microcode sequences they would be non-interruptible. We'd need one set of regs per potential CPU/thread context, and we'd also need to implement this in physical mem for the no-caches case (like ll/sc). More information can be found at the following URL: http://www.m5sim.org/flyspray/task/208 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
