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FS#261 - Make bus bridge use 1 line cache for partial block writes User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - Make bus bridge use 1 line cache for partial block writes Task Type - Bug Category - Memory System Status - New Assigned To - Ali Saidi Operating System - All Severity - High Priority - Normal Reported Version - 1.1 Due in Version - 2.0 Due Date - Undecided Percent Complete - 70% Details - Right now the bus bridge is doing a functional read when it sees a partial block write. It should really be using a 1 line cache to do it's work for it, but the caches probably need to be in a better state before this happens. This works now, however the implementation is non-ideal. We need more control over the latency on both sides of the cache. Generally, memory side requests should be handled quickly, while device side requests might take longer. However unless we stick another bus bridge between the devices and the cache this isn't really configurable. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/261 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
