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FS#270 - cache and bus reschedule on next tick instead of next clock User who did this: - Ali Saidi (saidi) Attached to Project - M5 Bugs Summary - cache and bus reschedule on next tick instead of next clock Task Type - Bug Category - Memory System Status - New Assigned To - Operating System - All Severity - Medium Priority - Normal Reported Version - 2.0beta2 Due in Version - 2.0 Due Date - Undecided Percent Complete - 0% Details - Lots of "retry" type events get scheduled at curTick+1 when they really should be scheduled for the next device clock edge (if not later). Requires adding the notion of a clock to the cache. Depends on new mechanism to be added for having per-object clocks. More information can be found at the following URL: http://www.m5sim.org/flyspray/task/270 You are receiving this message because you have requested it from the Flyspray bugtracking system. You can be removed from future notifications by visiting the URL shown above. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
