> changeset 09ab46bfa914 in /z/repo/m5 > details: http://repo.m5sim.org/m5?cmd=changeset;node=09ab46bfa914 > description: > InOrder: Import new inorder CPU model from MIPS. > This model currently only works in MIPS_SE mode, so it will take some > effort > to clean it up and make it generally useful. Hopefully people are > willing to > help make that happen!
Awesome! I've looked at this code quite a bit, and it's a great start, but I do think we need to put some effort into it to make it work well along with the other CPU models. My biggest concern is how registers, thread ids, and thread contexts are handled. This is different from other models. I'd really love it if we could have a call among people that really understand the CPU models so we can discuss what needs to be done to get things working. Unfortunately, I can't write huge amounts of code in this area because HP lawyers won't let me, but I can review patches, help tweak things, and in general give advice. My first inclination is that the InOrder model and MIPS should do threads the way the other ISAs and O3 do them, in that each hardware thread has a separate register file (as opposed to the unified register file done for MIPS), but we should certainly discuss the pros and cons of this. In general, I think our thread support is probably lacking, so coming up with a coordinated vision is a good thing. Anyone interested? Gabe? Kevin? Korey? Steve? I know that Daniel is interested in using the model. Anyone else out there want to pitch in? Nate _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
