Thanks for the helping in pushing this out Nate. There is a short and long version of the thread support in MIPS and why it varies.
I'll give the short version here: MIPS was implemented ot use the MT ISA extension which requires the ability to read/write registers from other threads. I designed the register file to be on size fits all. It can be instantiated multiple times as a per-thread register file (Simple-CPU) OR it could be used as one big physical register file to allow threads communicate with each other (InOrder model). This differs since O3 defines it's own physical register file instead of the pre-defined one in the src/arch folder. There is one patch that I need to send out that merges the two solutions together where I add a thread-ID to all the thread-context functions cpu/thread_context.* and then defaulted that value to 0. This in effect allowed the other ISAs (ALPHA/SPARC/etc.) to compile and run unaffected by the changes I made. I'm not sure the other ISAs will ever "care" about communicating between register files so I though that was an OK solution. (Well, I guess that version wasnt so short!) On Tue, Feb 10, 2009 at 7:12 PM, nathan binkert <n...@binkert.org> wrote: > > changeset 09ab46bfa914 in /z/repo/m5 > > details: http://repo.m5sim.org/m5?cmd=changeset;node=09ab46bfa914 > > description: > > InOrder: Import new inorder CPU model from MIPS. > > This model currently only works in MIPS_SE mode, so it will take > some effort > > to clean it up and make it generally useful. Hopefully people are > willing to > > help make that happen! > > > Awesome! I've looked at this code quite a bit, and it's a great > start, but I do think we need to put some effort into it to make it > work well along with the other CPU models. My biggest concern is how > registers, thread ids, and thread contexts are handled. This is > different from other models. I'd really love it if we could have a > call among people that really understand the CPU models so we can > discuss what needs to be done to get things working. Unfortunately, I > can't write huge amounts of code in this area because HP lawyers won't > let me, but I can review patches, help tweak things, and in general > give advice. > > My first inclination is that the InOrder model and MIPS should do > threads the way the other ISAs and O3 do them, in that each hardware > thread has a separate register file (as opposed to the unified > register file done for MIPS), but we should certainly discuss the pros > and cons of this. > > In general, I think our thread support is probably lacking, so coming > up with a coordinated vision is a good thing. > > Anyone interested? Gabe? Kevin? Korey? Steve? I know that Daniel is > interested in using the model. Anyone else out there want to pitch > in? > > Nate > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > -- ---------- Korey L Sewell Graduate Student - PhD Candidate Computer Science & Engineering University of Michigan
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