changeset ecebd7cccb06 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ecebd7cccb06
description:
X86: Fix segment override prefixes on instructions that use rbp/rsp and
a displacement.
diffstat:
4 files changed, 13 insertions(+), 5 deletions(-)
src/arch/x86/emulenv.cc | 3 +--
src/arch/x86/predecoder.cc | 3 +++
src/arch/x86/types.hh | 9 +++++++--
src/arch/x86/utility.hh | 3 ++-
diffs (83 lines):
diff -r 550f76603d41 -r ecebd7cccb06 src/arch/x86/emulenv.cc
--- a/src/arch/x86/emulenv.cc Sun Aug 02 18:01:13 2009 -0700
+++ b/src/arch/x86/emulenv.cc Mon Aug 03 11:01:40 2009 -0700
@@ -118,8 +118,7 @@
//Figure out what segment to use. This won't be entirely accurate since
//the presence of a displacement is supposed to make the instruction
//default to the data segment.
- if ((base != INTREG_RBP && base != INTREG_RSP) ||
- 0/*Has an immediate offset*/) {
+ if ((base != INTREG_RBP && base != INTREG_RSP) || machInst.dispSize) {
seg = SEGMENT_REG_DS;
//Handle any segment override that might have been in the instruction
int segFromInst = machInst.legacy.seg;
diff -r 550f76603d41 -r ecebd7cccb06 src/arch/x86/predecoder.cc
--- a/src/arch/x86/predecoder.cc Sun Aug 02 18:01:13 2009 -0700
+++ b/src/arch/x86/predecoder.cc Mon Aug 03 11:01:40 2009 -0700
@@ -77,6 +77,7 @@
immediateCollected = 0;
emi.immediate = 0;
emi.displacement = 0;
+ emi.dispSize = 0;
emi.modRM = 0;
emi.sib = 0;
@@ -383,6 +384,8 @@
emiIsReady = true;
nextState = ResetState;
}
+
+ emi.dispSize = displacementSize;
}
else
nextState = DisplacementState;
diff -r 550f76603d41 -r ecebd7cccb06 src/arch/x86/types.hh
--- a/src/arch/x86/types.hh Sun Aug 02 18:01:13 2009 -0700
+++ b/src/arch/x86/types.hh Mon Aug 03 11:01:40 2009 -0700
@@ -175,6 +175,8 @@
uint8_t addrSize;
//The effective stack size.
uint8_t stackSize;
+ //The size of the displacement
+ uint8_t dispSize;
//Mode information
OperatingMode mode;
@@ -187,12 +189,13 @@
"op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
"prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
"modRM = %#x,\n\tsib = %#x,\n\t"
- "immediate = %#x,\n\tdisplacement = %#x\n}\n",
+ "immediate = %#x,\n\tdisplacement = %#x\n\t"
+ "dispSize = %d}\n",
(uint8_t)emi.legacy, (uint8_t)emi.rex,
emi.opcode.num, (uint8_t)emi.opcode.op,
emi.opcode.prefixA, emi.opcode.prefixB,
(uint8_t)emi.modRM, (uint8_t)emi.sib,
- emi.immediate, emi.displacement);
+ emi.immediate, emi.displacement, emi.dispSize);
return os;
}
@@ -227,6 +230,8 @@
return false;
if(emi1.stackSize != emi2.stackSize)
return false;
+ if(emi1.dispSize != emi2.dispSize)
+ return false;
return true;
}
diff -r 550f76603d41 -r ecebd7cccb06 src/arch/x86/utility.hh
--- a/src/arch/x86/utility.hh Sun Aug 02 18:01:13 2009 -0700
+++ b/src/arch/x86/utility.hh Mon Aug 03 11:01:40 2009 -0700
@@ -82,7 +82,8 @@
((uint64_t)emi.opcode.op)) ^
emi.immediate ^ emi.displacement ^
emi.mode ^
- emi.opSize ^ emi.addrSize ^ emi.stackSize;
+ emi.opSize ^ emi.addrSize ^
+ emi.stackSize ^ emi.dispSize;
};
};
}
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
